main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers cd4027ns16ardq: viewers · Ray 5d ago
cd4027ns16ardq-etched.glb Publish 0.1.0 · Ray 5d ago
cd4027ns16ardq-etched.step cd4027ns16ardq: factory component page (tier=lcsc) · Ray 5d ago
cd4027ns16ardq-hero.glb cd4027ns16ardq: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
cd4027ns16ardq-hero.overlay.json Publish 0.1.0 · Ray 5d ago
cd4027ns16ardq.glb Publish 0.1.0 · Ray 5d ago
cd4027ns16ardq.kicad_mod Publish 0.1.0 · Ray 5d ago
cd4027ns16ardq.kicad_sym Publish 0.1.0 · Ray 5d ago
cd4027ns16ardq.lbr Publish 0.1.0 · Ray 5d ago
cd4027ns16ardq.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

CD4027NS16ARDQ

GR · Flip Flops · SOP-16

CD4027NS16ARDQ from GR, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q2 output Q output of flip-flop channel 2, the non-inverted output.
2 ~{Q2} output Inverted Q output of flip-flop channel 2.
3 CLOCK2 input Clock input for channel 2; state changes occur on the positive-going clock transition.
4 RESET2 input Reset input for channel 2; a high level sets Q low independent of the clock.
5 K2 input K input for channel 2, which with J2 determines the next state on the positive clock edge.
6 J2 input J input for channel 2, which with K2 determines the next state on the positive clock edge.
7 SET2 input Set input for channel 2; a high level sets Q high independent of the clock.
8 VSS power_in Ground reference (0 V); all voltages are referenced to this terminal.
9 SET1 input Set input for channel 1; a high level sets Q high independent of the clock.
10 J1 input J input for channel 1, which with K1 determines the next state on the positive clock edge.
11 K1 input K input for channel 1, which with J1 determines the next state on the positive clock edge.
12 RESET1 input Reset input for channel 1; a high level sets Q low independent of the clock.
13 CLOCK1 input Clock input for channel 1; state changes occur on the positive-going clock transition.
14 ~{Q1} output Inverted Q output of flip-flop channel 1.
15 Q1 output Q output of flip-flop channel 1, the non-inverted output.
16 VDD power_in Positive supply; the absolute maximum DC supply voltage is -0.5 V to 20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer GR
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range (referenced to VSS) VDD -0.5 20 V Voltage referenced to VSS terminals 3
Power Dissipation PD 500 mW 3
Junction Temperature TJ 125 ℃ 3
Operating Temperature TOP -40 85 ℃ 3
Low Level Output Current IOL 1 3 mA VO 0.4 V; VIN 0,5 V; VDD 5 V 4
Low Level Output Current IOL 4 8 mA VO 0.5 V; VIN 0,10 V; VDD 10 V 4
Low Level Output Current IOL 15 30 mA VO 1.5 V; VIN 0,15 V; VDD 15 V 4
High Level Output Current IOH -0.5 -1.5 mA VO 4.6 V; VIN 0,5 V; VDD 5 V 4
High Level Output Current IOH -3 -7 mA VO 2.5 V; VIN 0,5 V; VDD 5 V 4
High Level Output Current IOH -2 -4 mA VO 9.5 V; VIN 0,10 V; VDD 10 V 4
High Level Output Current IOH -7 -14 mA VO 13.5 V; VIN 0,15 V; VDD 15 V 4
Supply Current IDD 0 1 uA VIN 0,5 V; VDD 5 V 4
Low Level Output Voltage VOL 0 0.05 V VIN 0,5 V; VDD 5 V 4
High Level Output Voltage VOH 4.95 5 V VIN 0,5 V; VDD 5 V 4
High Level Output Voltage VOH 9.95 10 V VIN 0,10 V; VDD 10 V 4
High Level Output Voltage VOH 14.95 15 V VIN 0,15 V; VDD 15 V 4
Low Level Input Voltage VIL 1.5 V VO 0.5,4.5 V; VDD 5 V 4
Low Level Input Voltage VIL 3 V VO 1,9 V; VDD 10 V 4
Low Level Input Voltage VIL 4 V VO 1.5,13.5 V; VDD 15 V 4
High Level Input Voltage VIH 3.5 V VO 0.5,4.5 V; VDD 5 V 4
High Level Input Voltage VIH 7 V VO 1,9 V; VDD 10 V 4
High Level Input Voltage VIH 11 V VO 1.5,13.5 V; VDD 15 V 4
Input Leakage Current IIN -1 0 1 uA VIN 0 V; VDD 18 V 4

CAD (KiCad official)

  • Symbol: CD4027NS16ARDQ
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4027ns16ardq-etched.step / cd4027ns16ardq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4027ns16ardq.step / cd4027ns16ardq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GR datasheet (7 pp, sha256 2e3d824e36dd46ad, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF