component

CD4027BE

Public Made by Adom

by adom

Texas Instruments Flip Flops, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4027befactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd4027be / README.md
History Download
Ray Publish 0.1.0 e1180a9 3h ago

CD4027BE

Texas Instruments · Flip Flops · DIP-16

CD4027BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q2 output Q output for channel 2, buffered.
2 ~Q2 output Inverted Q output for channel 2, buffered.
3 CLOCK2 input Clock input for channel 2; flip-flop state changes are synchronous with the positive-going transition of the clock pulse.
4 RESET2 input Reset input for channel 2; a high level signal initiates reset independent of the clock.
5 K2 input K input for channel 2; together with J and internal self-steering it controls the flip-flop state at the clock transition.
6 J2 input J input for channel 2; together with K and internal self-steering it controls the flip-flop state at the clock transition.
7 SET2 input Set input for channel 2; a high level signal initiates set independent of the clock.
8 VSS power_in Ground reference; all voltages are referenced to the VSS terminal.
9 SET1 input Set input for channel 1; a high level signal initiates set independent of the clock.
10 J1 input J input for channel 1; together with K and internal self-steering it controls the flip-flop state at the clock transition.
11 K1 input K input for channel 1; together with J and internal self-steering it controls the flip-flop state at the clock transition.
12 RESET1 input Reset input for channel 1; a high level signal initiates reset independent of the clock.
13 CLOCK1 input Clock input for channel 1; flip-flop state changes are synchronous with the positive-going transition of the clock pulse.
14 ~Q1 output Inverted Q output for channel 1, buffered.
15 Q1 output Q output for channel 1, buffered.
16 VDD power_in Positive supply; the supply-voltage range is 3 V to 18 V over the full package-temperature range.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC Supply Voltage Range VDD -0.5 20 V Voltages referenced to VSS terminal 4
Input Voltage Range -0.5 V All inputs; upper limit printed as VDD + 0.5 V 4
DC Input Current -10 10 mA Any one input 4
Power Dissipation per Package PD 500 mW For TA = -55°C to +100°C 4
Power Dissipation per Package (derated range) PD 200 mW For TA = +100°C to +125°C; derate 12 mW/°C 4
Device Dissipation per Output Transistor 100 mW For TA = Full package-temperature range (all package types) 4
Operating Temperature Range TA -55 125 °C 4
Storage Temperature Tstg -65 150 °C 4
Lead Temperature (During Soldering) 265 °C At 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 s max 4
Supply-Voltage Range VDD 3 18 V For TA = Full package temperature range 4
Data Setup Time tS tS 200 ns VDD = 5 V 4
Data Setup Time tS tS 75 ns VDD = 10 V 4
Data Setup Time tS tS 50 ns VDD = 15 V 4
Clock Pulse Width tW tW 140 ns VDD = 5 V 4
Clock Pulse Width tW tW 60 ns VDD = 10 V 4
Clock Pulse Width tW tW 40 ns VDD = 15 V 4
Clock Input Frequency (Toggle Mode) fCL 3.5 MHz VDD = 5 V 4
Clock Input Frequency (Toggle Mode) fCL 8 MHz VDD = 10 V; min printed as dc 4
Clock Input Frequency (Toggle Mode) fCL 12 MHz VDD = 15 V 4
Clock Rise or Fall Time trCL, tfCL 45 μs VDD = 5 V 4
Clock Rise or Fall Time trCL, tfCL 5 μs VDD = 10 V 4
Clock Rise or Fall Time trCL, tfCL 2 μs VDD = 15 V 4
Set or Reset Pulse Width tW tW 180 ns VDD = 5 V 4
Set or Reset Pulse Width tW tW 80 ns VDD = 10 V 4
Set or Reset Pulse Width tW tW 50 ns VDD = 15 V 4
Quiescent Device Current IDD 0.02 1 μA VIN = 0, 5 V; VDD = 5 V; TA = +25°C 5
Quiescent Device Current IDD 0.02 2 μA VIN = 0, 10 V; VDD = 10 V; TA = +25°C 5
Quiescent Device Current IDD 0.02 4 μA VIN = 0, 15 V; VDD = 15 V; TA = +25°C 5
Quiescent Device Current IDD 0.04 20 μA VIN = 0, 20 V; VDD = 20 V; TA = +25°C 5
Quiescent Device Current IDD 30 μA VIN = 0, 5 V; VDD = 5 V; TA = +125°C 5
Quiescent Device Current IDD 60 μA VIN = 0, 10 V; VDD = 10 V; TA = +125°C 5
Quiescent Device Current IDD 120 μA VIN = 0, 15 V; VDD = 15 V; TA = +125°C 5
Quiescent Device Current IDD 600 μA VIN = 0, 20 V; VDD = 20 V; TA = +125°C 5
Output Low (Sink) Current IOL 0.51 1 mA VO = 0.4 V; VIN = 0, 5 V; VDD = 5 V; TA = +25°C 5
Output Low (Sink) Current IOL 1.3 2.6 mA VO = 0.5 V; VIN = 0, 10 V; VDD = 10 V; TA = +25°C 5
Output Low (Sink) Current IOL 3.4 6.8 mA VO = 1.5 V; VIN = 0, 15 V; VDD = 15 V; TA = +25°C 5
Output High (Source) Current IOH -0.51 -1 mA VO = 4.6 V; VIN = 0, 5 V; VDD = 5 V; TA = +25°C 5
Output High (Source) Current IOH -1.3 -2.6 mA VO = 9.5 V; VIN = 0, 10 V; VDD = 10 V; TA = +25°C 5
Output High (Source) Current IOH -3.4 -6.8 mA VO = 13.5 V; VIN = 0, 15 V; VDD = 15 V; TA = +25°C 5
Output Low-Level Voltage VOL 0 0.05 V VIN = 0, 5 V; VDD = 5 V 5
Output High-Level Voltage VOH 4.95 5 V VIN = 0, 5 V; VDD = 5 V 5
Output High-Level Voltage VOH 9.95 10 V VIN = 0, 10 V; VDD = 10 V 5
Output High-Level Voltage VOH 14.95 15 V VIN = 0, 15 V; VDD = 15 V 5
Input Low Voltage VIL 1.5 V VO = 0.5 V; VDD = 5 V 5
Input Low Voltage VIL 3 V VO = 1 V; VDD = 10 V 5
Input Low Voltage VIL 4 V VO = 1.5 V; VDD = 15 V 5
Input High Voltage VIH 3.5 V VO = 4.5 V; VDD = 5 V 5
Input High Voltage VIH 7 V VO = 9 V; VDD = 10 V 5
Input High Voltage VIH 11 V VO = 13.5 V; VDD = 15 V 5
Input Current IIH -0.1 0.1 μA VIN = 0, 18 V; VDD = 18 V; TA = +25°C 5
Input Current IIH -1 1 μA VIN = 0, 18 V; VDD = 18 V; TA = +125°C 5
Propagation Delay Time Clock to Q or Q Outputs tPHL, tPLH 150 300 ns VDD = 5 V; TA = 25°C; Input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ 5
Propagation Delay Time Clock to Q or Q Outputs tPHL, tPLH 65 130 ns VDD = 10 V; TA = 25°C; Input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ 5
Propagation Delay Time Clock to Q or Q Outputs tPHL, tPLH 45 90 ns VDD = 15 V; TA = 25°C; Input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ 5
Maximum Clock Input Frequency (Toggle Mode) fCL 3.5 7 MHz VDD = 5 V; TA = 25°C; Input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ 6
Maximum Clock Input Frequency (Toggle Mode) fCL 8 16 MHz VDD = 10 V; TA = 25°C; Input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ 6
Maximum Clock Input Frequency (Toggle Mode) fCL 12 24 MHz VDD = 15 V; TA = 25°C; Input tr, tf = 20 ns; CL = 50 pF; RL = 200 kΩ 6

CAD (KiCad official)

  • Symbol: CD4027BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4027be-etched.step / cd4027be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4027be.step / cd4027be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (25 pp, sha256 5e13a8ee723780e6, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF