component

CD4026BM

Public Made by Adom

by adom

lingxingic Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4026bmfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CD4026BM

lingxingic · Counters, Dividers · SOP-16

CD4026BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLK input Clock input; the function table shows the counter advancing on the rising edge of CLK when CLKN is LOW.
2 CLKN input Clock inhibit input; the function table shows it must be LOW for the counter to advance, and it is used with CLK for the falling-edge count.
3 DIS_EI input Display enable input; when LOW the decoded outputs are blanked (all segment outputs go LOW), per the function table.
4 DIS_EO output Display enable output, which goes LOW for the decade state that blanks the display, per the function table.
5 CARRY output Carry output that pulses to indicate the counter has reached the carry state, used to clock the next stage.
6 F output Segment output F of the decoded 7-segment display.
7 G output Segment output G of the decoded 7-segment display.
8 VSS power_in Ground supply voltage; all voltages are referenced to VSS (0 V).
9 D output Segment output D of the decoded 7-segment display.
10 A output Segment output A of the decoded 7-segment display.
11 E output Segment output E of the decoded 7-segment display.
12 B output Segment output B of the decoded 7-segment display.
13 C output Segment output C of the decoded 7-segment display.
14 UCS output Ungated C segment output, the C segment driven without display blanking, per the function table.
15 RST input Reset input; the function table shows the counter returns to 0 when RST is HIGH.
16 VDD power_in Supply voltage; the recommended operating range is 3 V to 15 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
HIGH-level input voltage (VDD=5V) VIH 3.5 V 7
HIGH-level input voltage (VDD=10V) VIH 7 V 7
HIGH-level input voltage (VDD=15V) VIH 11 V 7
LOW-level input voltage (VDD=5V) VIL 1.5 V 7
LOW-level input voltage (VDD=10V) VIL 3 V 7
LOW-level input voltage (VDD=15V) VIL 4 V 7
HIGH-level output voltage (VDD=5V) VOH 4.95 V /IO/<1uA 7
HIGH-level output voltage (VDD=10V) VOH 9.95 V /IO/<1uA 7
HIGH-level output voltage (VDD=15V) VOH 14.95 V /IO/<1uA 7
LOW-level output voltage (VDD=5V) VOL 0.05 V /IO/<1uA 7
LOW-level output voltage (VDD=10V) VOL 0.05 V /IO/<1uA 7
LOW-level output voltage (VDD=15V) VOL 0.05 V /IO/<1uA 7
HIGH-level output current (VDD=5V) IOH -0.3 mA VO=4.6V 7
HIGH-level output current (VDD=5V) IOH -1.15 mA VO=2.5V 7
HIGH-level output current (VDD=10V) IOH -0.45 mA VO=9.5V 7
HIGH-level output current (VDD=15V) IOH -1.4 mA VO=13.5V 7
LOW-level output current (VDD=5V) IOL 0.29 mA VO=0.4V 7
LOW-level output current (VDD=10V) IOL 0.38 mA VO=0.5V 7
LOW-level output current (VDD=15V) IOL 1.2 mA VO=1.5V 7
input leakage current (VDD=15V) II -4 4 uA VI=15V or GND 7
supply current (VDD=5V) IDD 7.5 uA VI=5V or GND; IO=0A 7
supply current (VDD=10V) IDD 15 uA VI=10V or GND; IO=0A 7
supply current (VDD=15V) IDD 30 uA VI=15V or GND; IO=0A 7
propagation delay time, clocked, carry-out line (VDD=5V) tPHL, tPLH 600 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, clocked, carry-out line (VDD=10V) tPHL, tPLH 240 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, clocked, carry-out line (VDD=15V) tPHL, tPLH 180 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, clocked, decode outline (VDD=5V) tPHL, tPLH 840 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, clocked, decode outline (VDD=10V) tPHL, tPLH 300 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, clocked, decode outline (VDD=15V) tPHL, tPLH 216 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, reset, carry-out line (VDD=5V) tPHL, tPLH 660 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, reset, carry-out line (VDD=10V) tPHL, tPLH 288 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, reset, carry-out line (VDD=15V) tPHL, tPLH 192 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, reset, decode outline (VDD=5V) tPLH 720 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, reset, decode outline (VDD=10V) tPLH 300 ns CL=50pF, RL=200kΩ, see Figure 4 9
propagation delay time, reset, decode outline (VDD=15V) tPLH 216 ns CL=50pF, RL=200kΩ, see Figure 4 9
transition time (VDD=5V) tTHL, tTLH 240 ns CL=50pF, RL=200kΩ, see Figure 4 9
transition time (VDD=10V) tTHL, tTLH 120 ns CL=50pF, RL=200kΩ, see Figure 4 9
transition time (VDD=15V) tTHL, tTLH 60 ns CL=50pF, RL=200kΩ, see Figure 4 9
Minimum clock pulse width HIGH (VDD=5V) tWCPH 264 ns 9
Minimum clock pulse width HIGH (VDD=10V) tWCPH 120 ns 9
Minimum clock pulse width HIGH (VDD=15V) tWCPH 96 ns 9
Minimum MR pulse width HIGH (VDD=5V) tWMRH 144 ns 9
Minimum MR pulse width HIGH (VDD=10V) tWMRH 120 ns 9
Minimum MR pulse width HIGH (VDD=15V) tWMRH 60 ns 9
Maximum clock pulse frequency (VDD=5V) fmax 4 MHZ 9
Maximum clock pulse frequency (VDD=10V) fmax 8 MHZ 9
Maximum clock pulse frequency (VDD=15V) fmax 12 MHZ 9
supply voltage (absolute maximum) VDD -0.5 18 V 6
input voltage, all inputs (absolute maximum; printed max is VDD+0.5) VI -0.5 V all inputs 6
DC input current, any one input (absolute maximum) IIK -10 10 mA any one input 6
storage temperature (absolute maximum) Tstg -65 150 ℃ 6
soldering temperature (absolute maximum, SOP/TSSOP) TL 260 ℃ 10s 6
supply voltage (recommended operating) VDD 3 15 V 6
ambient temperature (recommended operating) Tamb -40 125 ℃ in free air 6

CAD (KiCad official)

  • Symbol: CD4026BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4026bm-etched.step / cd4026bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4026bm.step / cd4026bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 47fc3c66e3dd6817, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF