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CD4025BE

Public Made by Adom

by adom

lingxingic Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4025BE

lingxingic · Logic Gates · DIP-14

CD4025BE from lingxingic, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 2A input Data input 2A of NOR gate 2; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
2 2B input Data input 2B of NOR gate 2; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
3 1A input Data input 1A of NOR gate 1; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
4 1B input Data input 1B of NOR gate 1; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
5 1C input Data input 1C of NOR gate 1; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
6 1Y output Buffered data output 1Y of NOR gate 1.
7 VSS power_in Ground reference pin, 0 V; all voltages are referenced to VSS.
8 2C input Data input 2C of NOR gate 2; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
9 2Y output Buffered data output 2Y of NOR gate 2.
10 3Y output Buffered data output 3Y of NOR gate 3.
11 3A input Data input 3A of NOR gate 3; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
12 3B input Data input 3B of NOR gate 3; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
13 3C input Data input 3C of NOR gate 3; the input voltage must stay between -0.5 V and VDD+0.5 V (absolute maximum).
14 VDD power_in Supply voltage pin; recommended operating range is 3 V to 15 V referenced to VSS, absolute maximum 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 5
DC input current IIK -10 10 mA any one input 5
input voltage VI -0.5 V all inputs; upper limit printed as VDD+0.5 V 5
storage temperature Tstg -65 150 ℃ 5
total power dissipation Ptot 500 mW 5
device dissipation per output transistor P 100 mW per output transistor 5
soldering temperature TL 245 ℃ 10s DIP 5
supply voltage VDD 3 15 V 6
ambient temperature Tamb -40 125 ℃ in free air 6
supply current IDD 1 uA VO -, VIN 0,5, VDD 5 V, Tamb=25℃ 6
LOW-level output current IOL 0.51 1 mA VO 0.4, VIN 0,5, VDD 5 V, Tamb=25℃ 6
LOW-level output current IOL 1.3 2.6 mA VO 0.5, VIN 0,10, VDD 10 V, Tamb=25℃ 6
LOW-level output current IOL 3.4 6.8 mA VO 1.5, VIN 0,15, VDD 15 V, Tamb=25℃ 6
HIGH-level output current IOH -0.51 -1 mA VO 4.6, VIN 0,5, VDD 5 V, Tamb=25℃ 6
HIGH-level output current IOH -1.6 -3.2 mA VO 2.5, VIN 0,5, VDD 5 V, Tamb=25℃ 6
HIGH-level output current IOH -1.3 -2.6 mA VO 9.5, VIN 0,10, VDD 10 V, Tamb=25℃ 6
HIGH-level output current IOH -3.4 -6.8 mA VO 13.5, VIN 0,15, VDD 15 V, Tamb=25℃ 6
LOW-level output voltage VOL 0 0.05 V VO -, VIN 0,5, VDD 5 V, Tamb=25℃ 6
HIGH-level output voltage VOH 4.95 5 V VO -, VIN 0,5, VDD 5 V, Tamb=25℃ 6
HIGH-level output voltage VOH 9.95 10 V VO -, VIN 0,10, VDD 10 V, Tamb=25℃ 6
HIGH-level output voltage VOH 14.95 15 V VO -, VIN 0,15, VDD 15 V, Tamb=25℃ 6
LOW-level input voltage VIL 1.5 V VO 0.5,4.5, VIN -, VDD 5 V, Tamb=25℃ 6
LOW-level input voltage VIL 3 V VO 1,9, VIN -, VDD 10 V, Tamb=25℃ 6
LOW-level input voltage VIL 4 V VO 1.5,13.5, VIN -, VDD 15 V, Tamb=25℃ 6
HIGH-level input voltage VIH 3.5 V VO 0.5, VIN -, VDD 5 V, Tamb=25℃ 6
HIGH-level input voltage VIH 7 V VO 1, VIN -, VDD 10 V, Tamb=25℃ 6
HIGH-level input voltage VIH 11 V VO 1.5, VIN -, VDD 15 V, Tamb=25℃ 6
input leakage current II -1 1 uA VO -, VIN 0,15, VDD 15 V, Tamb=25℃ 6
supply current IDD 7.5 uA VO -, VIN 0,5, VDD 5 V, Tamb=+125℃ 7
supply current IDD 15 uA VO -, VIN 0,10, VDD 10 V, Tamb=+125℃ 7
supply current IDD 30 uA VO -, VIN 0,15, VDD 15 V, Tamb=+125℃ 7
LOW-level output current IOL 0.36 mA VO 0.4, VIN 0,5, VDD 5 V, Tamb=+125℃ 7
LOW-level output current IOL 0.9 mA VO 0.5, VIN 0,10, VDD 10 V, Tamb=+125℃ 7
LOW-level output current IOL 2.4 mA VO 1.5, VIN 0,15, VDD 15 V, Tamb=+125℃ 7
HIGH-level output current IOH -0.36 mA VO 4.6, VIN 0,5, VDD 5 V, Tamb=+125℃ 7
HIGH-level output current IOH -0.9 mA VO 9.5, VIN 0,10, VDD 10 V, Tamb=+125℃ 7
HIGH-level output current IOH -2.4 mA VO 13.5, VIN 0,15, VDD 15 V, Tamb=+125℃ 7
LOW-level output voltage VOL 0.05 V VO -, VIN 0,5, VDD 5 V, Tamb=+125℃ 7
HIGH-level output voltage VOH 4.95 V VO -, VIN 0,5, VDD 5 V, Tamb=+125℃ 7
HIGH-level output voltage VOH 9.95 V VO -, VIN 0,10, VDD 10 V, Tamb=+125℃ 7
HIGH-level output voltage VOH 14.95 V VO -, VIN 0,15, VDD 15 V, Tamb=+125℃ 7
LOW-level input voltage VIL 1.5 V VO 0.5,4.5, VIN -, VDD 5 V, Tamb=+125℃ 7
LOW-level input voltage VIL 3 V VO 1,9, VIN -, VDD 10 V, Tamb=+125℃ 7
LOW-level input voltage VIL 4 V VO 1.5,13.5, VIN -, VDD 15 V, Tamb=+125℃ 7
HIGH-level input voltage VIH 3.5 V VO 0.5, VIN -, VDD 5 V, Tamb=+125℃ 7
HIGH-level input voltage VIH 7 V VO 1, VIN -, VDD 10 V, Tamb=+125℃ 7
HIGH-level input voltage VIH 11 V VO 1.5, VIN -, VDD 15 V, Tamb=+125℃ 7
propagation delay time tPHL, tPLH 125 250 ns see Figure 4, VDD=5V, Tamb=25℃ 7
propagation delay time tPHL, tPLH 60 120 ns see Figure 4, VDD=10V, Tamb=25℃ 7
propagation delay time tPHL, tPLH 45 90 ns see Figure 4, VDD=15V, Tamb=25℃ 7
transition time tTHL, tTLH 100 200 ns see Figure 4, VDD=5V, Tamb=25℃ 7
transition time tTHL, tTLH 50 100 ns see Figure 4, VDD=10V, Tamb=25℃ 7
transition time tTHL, tTLH 40 80 ns see Figure 4, VDD=15V, Tamb=25℃ 7
input capacitance CI 5 7.5 pF any input 7

CAD (KiCad official)

  • Symbol: CD4025BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4025be-etched.step / cd4025be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4025be.step / cd4025be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (12 pp, sha256 ef6f940e79549369, retrieved 2026-10-14, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF