CD4025B Triple NOR Gate

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4025",
  "title": "CD4025B Triple NOR Gate",
  "brief": "Triple NOR Gate in the 4000B CMOS family, 3 V to 18 V.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "logic",
    "gate",
    "4000-series",
    "cmos",
    "ti",
    "soic-14"
  ],
  "component": {
    "mpn": "CD4025B",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gate",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4025b.pdf",
    "parts": {
      "symbol": "cd4025.kicad_sym",
      "footprint": "cd4025.kicad_mod",
      "model_3d": "cd4025-etched.glb",
      "model_3d_plain": "cd4025.glb",
      "model_3d_step": "cd4025-etched.step",
      "model_3d_step_plain": "cd4025.step",
      "lbr": "cd4025.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "1A",
        "type": "input",
        "description": "Gate 1 input A. High-impedance CMOS input with internal protection diodes. Input high level VIH = 3.5 V (at VDD=5 V) / 11 V (at VDD=15 V)."
      },
      {
        "number": "2",
        "name": "1B",
        "type": "input",
        "description": "Gate 1 input B. High-impedance CMOS input; all three gate-1 inputs are ORed then inverted to produce output Y1 on pin 9."
      },
      {
        "number": "3",
        "name": "2A",
        "type": "input",
        "description": "Gate 2 input A. High-impedance CMOS input; contributes to NOR output Y2 on pin 6."
      },
      {
        "number": "4",
        "name": "2B",
        "type": "input",
        "description": "Gate 2 input B. High-impedance CMOS input; contributes to NOR output Y2 on pin 6."
      },
      {
        "number": "5",
        "name": "2C",
        "type": "input",
        "description": "Gate 2 input C. High-impedance CMOS input; contributes to NOR output Y2 on pin 6."
      },
      {
        "number": "6",
        "name": "2Y",
        "type": "output",
        "description": "Gate 2 output = NOR(2A, 2B, 2C). Buffered CMOS push-pull output; IOL/IOH ≈ 1 mA typical at VDD=10 V."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference. Normally tied to 0 V; all input and output voltages are referenced to VSS."
      },
      {
        "number": "8",
        "name": "1C",
        "type": "input",
        "description": "Gate 1 input C. High-impedance CMOS input; contributes to NOR output Y1 on pin 9."
      },
      {
        "number": "9",
        "name": "1Y",
        "type": "output",
        "description": "Gate 1 output = NOR(1A, 1B, 1C). Buffered CMOS push-pull output; symmetrical source/sink drive."
      },
      {
        "number": "10",
        "name": "3Y",
        "type": "output",
        "description": "Gate 3 output = NOR(3A, 3B, 3C). Buffered CMOS push-pull output."
      },
      {
        "number": "11",
        "name": "3A",
        "type": "input",
        "description": "Gate 3 input A. High-impedance CMOS input; contributes to NOR output Y3 on pin 10."
      },
      {
        "number": "12",
        "name": "3B",
        "type": "input",
        "description": "Gate 3 input B. High-impedance CMOS input; contributes to NOR output Y3 on pin 10."
      },
      {
        "number": "13",
        "name": "3C",
        "type": "input",
        "description": "Gate 3 input C. High-impedance CMOS input; contributes to NOR output Y3 on pin 10."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply. Recommended operating range 3 V to 18 V (absolute max 20 V). All inputs are protected by CMOS input protection network referenced between VDD and VSS."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd4025b.pdf",
        "pages": 23,
        "sha256": "d33d12a8e68dd293",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4025",
      "logic_family": "CD4000",
      "function_code": "4025",
      "function_class": null,
      "function_name": null,
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4025.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          8.7,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4025-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "4fe60d83752c23f2da874d7ddf175423c193138cdd225aacf3c0a821fc7b05af",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Type": "Triple NOR Gate",
      "Logic family": "4000B (CMOS)",
      "Supply voltage": "3 V to 18 V",
      "Propagation delay": "45 ns typ at 10 V",
      "Operating temperature": "-55 C to 125 C"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "Triple NOR Gate",
    "CMOS logic",
    "wide-voltage logic",
    "glue logic"
  ],
  "discovery_pitch": "The CD4025B contains three independent 3-input NOR gates; each output is high only when all three inputs are low.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
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    "README.md",
    "cd4025.kicad_sym",
    "cd4025.kicad_mod",
    "cd4025.glb",
    "cd4025.step",
    "cd4025.lbr",
    "docs/hero.png",
    "docs/cd4025-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4025-etched.step"
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  "variants": [
    {
      "mpn": "CD4025BE",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBE",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBE.A",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBEE4",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BF",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBF",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBF3A",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BF3A",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BM",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBM",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBM96",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBMT",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BNSR",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBNSR",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BPW",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BPWR",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BPWE4",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBPW",
      "kind": "unknown"
    },
    {
      "mpn": "CD4025BBPWR",
      "kind": "unknown"
    }
  ]
}