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CD4025B Triple NOR Gate
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Triple NOR Gate in the 4000B CMOS family, 3 V to 18 V.
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CD4025B
Texas Instruments · Logic Gate · SOIC-14
The CD4025B contains three independent 3-input NOR gates; each output is high only when all three inputs are low. It runs from 3 V to 18 V, part of the 4000B CMOS logic family.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A. High-impedance CMOS input with internal protection diodes. Input high level VIH = 3.5 V (at VDD=5 V) / 11 V (at VDD=15 V). |
| 2 | 1B | input | Gate 1 input B. High-impedance CMOS input; all three gate-1 inputs are ORed then inverted to produce output Y1 on pin 9. |
| 3 | 2A | input | Gate 2 input A. High-impedance CMOS input; contributes to NOR output Y2 on pin 6. |
| 4 | 2B | input | Gate 2 input B. High-impedance CMOS input; contributes to NOR output Y2 on pin 6. |
| 5 | 2C | input | Gate 2 input C. High-impedance CMOS input; contributes to NOR output Y2 on pin 6. |
| 6 | 2Y | output | Gate 2 output = NOR(2A, 2B, 2C). Buffered CMOS push-pull output; IOL/IOH ≈ 1 mA typical at VDD=10 V. |
| 7 | VSS | power_in | Negative supply / ground reference. Normally tied to 0 V; all input and output voltages are referenced to VSS. |
| 8 | 1C | input | Gate 1 input C. High-impedance CMOS input; contributes to NOR output Y1 on pin 9. |
| 9 | 1Y | output | Gate 1 output = NOR(1A, 1B, 1C). Buffered CMOS push-pull output; symmetrical source/sink drive. |
| 10 | 3Y | output | Gate 3 output = NOR(3A, 3B, 3C). Buffered CMOS push-pull output. |
| 11 | 3A | input | Gate 3 input A. High-impedance CMOS input; contributes to NOR output Y3 on pin 10. |
| 12 | 3B | input | Gate 3 input B. High-impedance CMOS input; contributes to NOR output Y3 on pin 10. |
| 13 | 3C | input | Gate 3 input C. High-impedance CMOS input; contributes to NOR output Y3 on pin 10. |
| 14 | VDD | power_in | Positive supply. Recommended operating range 3 V to 18 V (absolute max 20 V). All inputs are protected by CMOS input protection network referenced between VDD and VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Type | Triple NOR Gate |
| Logic family | 4000B (CMOS) |
| Supply voltage | 3 V to 18 V |
| Propagation delay | 45 ns typ at 10 V |
| Operating temperature | -55 C to 125 C |
Ordering variants
Same part, different packaging or reel option.
CD4025BECD4025BBECD4025BBE.ACD4025BBEE4CD4025BFCD4025BBFCD4025BBF3ACD4025BF3ACD4025BMCD4025BBMCD4025BBM96CD4025BBMTCD4025BNSRCD4025BBNSRCD4025BPWCD4025BPWRCD4025BPWE4CD4025BBPWCD4025BBPWR
CAD (KiCad official)
- Symbol:
cd4025.kicad_sym - Footprint:
cd4025.kicad_mod - 3D model: SOIC-14 body from KiCad
Package_SO/SOIC-14_3.9x8.7mm_P1.27mm. - 3D model files:
cd4025-etched.step/cd4025-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4025.step/cd4025.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
d33d12a8e68dd293, retrieved 2026-08-17, tier: manufacturer) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4025B
**Texas Instruments** · Logic Gate · SOIC-14
The CD4025B contains three independent 3-input NOR gates; each output is high only when all three inputs are low. It runs from 3 V to 18 V, part of the 4000B CMOS logic family.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1A | input | Gate 1 input A. High-impedance CMOS input with internal protection diodes. Input high level VIH = 3.5 V (at VDD=5 V) / 11 V (at VDD=15 V). |
| 2 | 1B | input | Gate 1 input B. High-impedance CMOS input; all three gate-1 inputs are ORed then inverted to produce output Y1 on pin 9. |
| 3 | 2A | input | Gate 2 input A. High-impedance CMOS input; contributes to NOR output Y2 on pin 6. |
| 4 | 2B | input | Gate 2 input B. High-impedance CMOS input; contributes to NOR output Y2 on pin 6. |
| 5 | 2C | input | Gate 2 input C. High-impedance CMOS input; contributes to NOR output Y2 on pin 6. |
| 6 | 2Y | output | Gate 2 output = NOR(2A, 2B, 2C). Buffered CMOS push-pull output; IOL/IOH ≈ 1 mA typical at VDD=10 V. |
| 7 | VSS | power_in | Negative supply / ground reference. Normally tied to 0 V; all input and output voltages are referenced to VSS. |
| 8 | 1C | input | Gate 1 input C. High-impedance CMOS input; contributes to NOR output Y1 on pin 9. |
| 9 | 1Y | output | Gate 1 output = NOR(1A, 1B, 1C). Buffered CMOS push-pull output; symmetrical source/sink drive. |
| 10 | 3Y | output | Gate 3 output = NOR(3A, 3B, 3C). Buffered CMOS push-pull output. |
| 11 | 3A | input | Gate 3 input A. High-impedance CMOS input; contributes to NOR output Y3 on pin 10. |
| 12 | 3B | input | Gate 3 input B. High-impedance CMOS input; contributes to NOR output Y3 on pin 10. |
| 13 | 3C | input | Gate 3 input C. High-impedance CMOS input; contributes to NOR output Y3 on pin 10. |
| 14 | VDD | power_in | Positive supply. Recommended operating range 3 V to 18 V (absolute max 20 V). All inputs are protected by CMOS input protection network referenced between VDD and VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Type | Triple NOR Gate |
| Logic family | 4000B (CMOS) |
| Supply voltage | 3 V to 18 V |
| Propagation delay | 45 ns typ at 10 V |
| Operating temperature | -55 C to 125 C |
## Ordering variants
Same part, different packaging or reel option.
- `CD4025BE`
- `CD4025BBE`
- `CD4025BBE.A`
- `CD4025BBEE4`
- `CD4025BF`
- `CD4025BBF`
- `CD4025BBF3A`
- `CD4025BF3A`
- `CD4025BM`
- `CD4025BBM`
- `CD4025BBM96`
- `CD4025BBMT`
- `CD4025BNSR`
- `CD4025BBNSR`
- `CD4025BPW`
- `CD4025BPWR`
- `CD4025BPWE4`
- `CD4025BBPW`
- `CD4025BBPWR`
## CAD (KiCad official)
- Symbol: `cd4025.kicad_sym`
- Footprint: `cd4025.kicad_mod`
- 3D model: SOIC-14 body from KiCad `Package_SO/SOIC-14_3.9x8.7mm_P1.27mm`.
- 3D model files: `cd4025-etched.step` / `cd4025-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4025.step` / `cd4025.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4025b.pdf) (23 pp, sha256 `d33d12a8e68dd293`, retrieved 2026-08-17, tier: manufacturer)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4025-datasheet.pdf)