component

CD4024BE

Public Made by Adom

by adom

lingxingic Counters, Dividers, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4024befactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers cd4024be: viewers · Ray 5d ago
cd4024be-etched.glb Publish 0.1.0 · Ray 5d ago
cd4024be-etched.step cd4024be: factory component page (tier=lcsc) · Ray 5d ago
cd4024be-hero.glb cd4024be: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
cd4024be-hero.overlay.json Publish 0.1.0 · Ray 5d ago
cd4024be.glb Publish 0.1.0 · Ray 5d ago
cd4024be.kicad_mod Publish 0.1.0 · Ray 5d ago
cd4024be.kicad_sym Publish 0.1.0 · Ray 5d ago
cd4024be.lbr Publish 0.1.0 · Ray 5d ago
cd4024be.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

CD4024BE

lingxingic · Counters, Dividers · DIP-14

CD4024BE from lingxingic, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CP input Clock input; the counter advances to the next state on the HIGH-to-LOW transition of CP.
2 MR input Master reset; a HIGH level clears all counter outputs to LOW regardless of CP.
3 O6 output Buffered parallel output O6.
4 O5 output Buffered parallel output O5.
5 O4 output Buffered parallel output O4.
6 O3 output Buffered parallel output O3.
7 VSS power_in Ground supply voltage (0 V reference).
8 NC unconnected Not connected.
9 O2 output Buffered parallel output O2.
10 NC unconnected Not connected.
11 O1 output Buffered parallel output O1.
12 O0 output Buffered parallel output O0.
13 NC unconnected Not connected.
14 VDD power_in Supply voltage, recommended 3 V to 15 V (absolute maximum 18 V).

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V referenced to VSS 5
Input voltage VI -0.5 V all inputs; max printed as VDD+0.5 5
DC input current IIK -10 10 mA any one input 5
Storage temperature Tstg -65 150 ℃ 5
Soldering temperature DIP TL 245 ℃ 10s, DIP 5
Supply voltage VDD 3 15 V 5
Ambient temperature Tamb -40 125 ℃ in free air 5
HIGH-level input voltage VIH 3.5 V VDD=5V, Tamb=-40℃ to +85℃ 5
HIGH-level input voltage VIH 7 V VDD=10V, Tamb=-40℃ to +85℃ 5
HIGH-level input voltage VIH 11 V VDD=15V, Tamb=-40℃ to +85℃ 5
LOW-level input voltage VIL 1.5 V VDD=5V, Tamb=-40℃ to +85℃ 5
LOW-level input voltage VIL 3 V VDD=10V, Tamb=-40℃ to +85℃ 5
LOW-level input voltage VIL 4 V VDD=15V, Tamb=-40℃ to +85℃ 5
HIGH-level output voltage VOH 4.95 V VDD=5V, /IO/<1uA, Tamb=-40℃ to +85℃ 5
HIGH-level output voltage VOH 9.95 V VDD=10V, /IO/<1uA, Tamb=-40℃ to +85℃ 5
HIGH-level output voltage VOH 14.95 V VDD=15V, /IO/<1uA, Tamb=-40℃ to +85℃ 5
LOW-level output voltage VOL 0.05 V VDD=5V, /IO/<1uA, Tamb=-40℃ to +85℃ 5
HIGH-level output current IOH -0.34 mA VDD=5V, VO=4.6V, Tamb=-40℃ to +85℃ 5
HIGH-level output current IOH -1.3 mA VDD=5V, VO=2.5V, Tamb=-40℃ to +85℃ 5
HIGH-level output current IOH -0.55 mA VDD=10V, VO=9.5V, Tamb=-40℃ to +85℃ 5
HIGH-level output current IOH -1.65 mA VDD=15V, VO=13.5V, Tamb=-40℃ to +85℃ 5
LOW-level output current IOL 0.34 mA VDD=5V, VO=0.4V, Tamb=-40℃ to +85℃ 6
LOW-level output current IOL 0.46 mA VDD=10V, VO=0.5V, Tamb=-40℃ to +85℃ 6
LOW-level output current IOL 1.4 mA VDD=15V, VO=1.5V, Tamb=-40℃ to +85℃ 6
Input leakage current II -2 2 uA VDD=15V, VI=15V or GND, Tamb=-40℃ to +85℃ 6
Supply current IDD 7.5 uA VDD=5V, VI=5V or GND; IO=0A, Tamb=-40℃ to +85℃ 6
Supply current IDD 15 uA VDD=10V, VI=10V or GND; IO=0A, Tamb=-40℃ to +85℃ 6
Supply current IDD 30 uA VDD=15V, VI=15V or GND; IO=0A, Tamb=-40℃ to +85℃ 6
On to On+1 HIGH to LOW propagation delay tPHL 60 120 ns VDD=5V, CL=50pF, Tamb=-40℃ to +85℃ 7
On to On+1 HIGH to LOW propagation delay tPHL 25 50 ns VDD=10V, CL=50pF, Tamb=-40℃ to +85℃ 7
On to On+1 HIGH to LOW propagation delay tPHL 20 40 ns VDD=15V, CL=50pF, Tamb=-40℃ to +85℃ 7
On to On+1 LOW to HIGH propagation delay tPLH 50 100 ns VDD=5V, CL=50pF, Tamb=-40℃ to +85℃ 7
On to On+1 LOW to HIGH propagation delay tPLH 20 40 ns VDD=10V, CL=50pF, Tamb=-40℃ to +85℃ 7
On to On+1 LOW to HIGH propagation delay tPLH 15 30 ns VDD=15V, CL=50pF, Tamb=-40℃ to +85℃ 7
CP to O0 HIGH to LOW propagation delay tPHL 100 200 ns VDD=5V, CL=50pF, Tamb=-40℃ to +85℃ 7
CP to O0 HIGH to LOW propagation delay tPHL 40 75 ns VDD=10V, CL=50pF, Tamb=-40℃ to +85℃ 7
CP to O0 HIGH to LOW propagation delay tPHL 25 50 ns VDD=15V, CL=50pF, Tamb=-40℃ to +85℃ 7
CP to O0 LOW to HIGH propagation delay tPLH 105 210 ns VDD=5V, CL=50pF, Tamb=-40℃ to +85℃ 7
CP to O0 LOW to HIGH propagation delay tPLH 45 85 ns VDD=10V, CL=50pF, Tamb=-40℃ to +85℃ 7
CP to O0 LOW to HIGH propagation delay tPLH 30 60 ns VDD=15V, CL=50pF, Tamb=-40℃ to +85℃ 7
MR to Qn HIGH to LOW propagation delay tPHL 120 240 ns VDD=5V, CL=50pF, Tamb=-40℃ to +85℃ 7
MR to Qn HIGH to LOW propagation delay tPHL 45 90 ns VDD=10V, CL=50pF, Tamb=-40℃ to +85℃ 7
MR to Qn HIGH to LOW propagation delay tPHL 30 60 ns VDD=15V, CL=50pF, Tamb=-40℃ to +85℃ 7
Transition time tTHL, tTLH 60 120 ns VDD=5V, CL=50pF, Tamb=-40℃ to +85℃ 7
Transition time tTHL, tTLH 30 60 ns VDD=10V, CL=50pF, Tamb=-40℃ to +85℃ 7
Transition time tTHL, tTLH 20 40 ns VDD=15V, CL=50pF, Tamb=-40℃ to +85℃ 7
Minimum clock pulse width; HIGH tWCPH 60 120 ns VDD=5V, see Figure 5, Tamb=-40℃ to +85℃ 7
Minimum clock pulse width; HIGH tWCPH 30 60 ns VDD=10V, see Figure 5, Tamb=-40℃ to +85℃ 7
Minimum clock pulse width; HIGH tWCPH 20 40 ns VDD=15V, see Figure 5, Tamb=-40℃ to +85℃ 7
Minimum MR pulse width; HIGH tWMRH 80 40 ns VDD=5V, see Figure 5, Tamb=-40℃ to +85℃ 7
Minimum MR pulse width; HIGH tWMRH 35 20 ns VDD=10V, see Figure 5, Tamb=-40℃ to +85℃ 7
Minimum MR pulse width; HIGH tWMRH 25 15 ns VDD=15V, see Figure 5, Tamb=-40℃ to +85℃ 7
Recovery time for MR tRMR 20 10 ns VDD=5V, see Figure 5, Tamb=-40℃ to +85℃ 7
Recovery time for MR tRMR 15 5 ns VDD=10V, see Figure 5, Tamb=-40℃ to +85℃ 7
Maximum clock pulse frequency fmax 5 10 MHZ VDD=5V, Tamb=-40℃ to +85℃ 7
Maximum clock pulse frequency fmax 13 25 MHZ VDD=10V, Tamb=-40℃ to +85℃ 7
Maximum clock pulse frequency fmax 18 35 MHZ VDD=15V, Tamb=-40℃ to +85℃ 7

CAD (KiCad official)

  • Symbol: CD4024BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4024be-etched.step / cd4024be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4024be.step / cd4024be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (14 pp, sha256 a14d39dcbd5cd7f0, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF