# CD4023BPWR

**Texas Instruments** · Logic Gates · TSSOP-14

CD4023BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gate 1 input A, NAND input for J = NOT(A·B·C), buffered CMOS input. |
| 2 | B | input | Gate 1 input B, NAND input for J = NOT(A·B·C), buffered CMOS input. |
| 3 | D | input | Gate 2 input D, NAND input for K = NOT(D·E·F), buffered CMOS input. |
| 4 | E | input | Gate 2 input E, NAND input for K = NOT(D·E·F), buffered CMOS input. |
| 5 | F | input | Gate 2 input F, NAND input for K = NOT(D·E·F), buffered CMOS input. |
| 6 | K | output | Gate 2 output K = NOT(D·E·F), buffered output. |
| 7 | VSS | power_in | Ground / negative supply terminal; all voltages are referenced to VSS. |
| 8 | C | input | Gate 1 input C, NAND input for J = NOT(A·B·C), buffered CMOS input. |
| 9 | J | output | Gate 1 output J = NOT(A·B·C), buffered output. |
| 10 | L | output | Gate 3 output L = NOT(G·H·I), buffered output. |
| 11 | I | input | Gate 3 input I, NAND input for L = NOT(G·H·I), buffered CMOS input. |
| 12 | H | input | Gate 3 input H, NAND input for L = NOT(G·H·I), buffered CMOS input. |
| 13 | G | input | Gate 3 input G, NAND input for L = NOT(G·H·I), buffered CMOS input. |
| 14 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `CD4023BPWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4023bpwr-etched.step` / `cd4023bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4023bpwr.step` / `cd4023bpwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4023b.pdf) (23 pp, sha256 `6c17dba0a390eb11`, retrieved 2026-10-08, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4023bpwr-datasheet.pdf)