CD4021BM96

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4021bm96",
  "title": "CD4021BM96",
  "brief": "Texas Instruments Shifting Register, SOIC-16. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4021bm96"
  ],
  "component": {
    "mpn": "CD4021BM96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Shifting Register",
    "datasheet": "https://www.ti.com/lit/ds/symlink/cd4021bm96.pdf",
    "parts": {
      "symbol": "cd4021bm96.kicad_sym",
      "footprint": "cd4021bm96.kicad_mod",
      "model_3d": "cd4021bm96-etched.glb",
      "model_3d_plain": "cd4021bm96.glb",
      "model_3d_step": "cd4021bm96-etched.step",
      "model_3d_step_plain": "cd4021bm96.step",
      "lbr": "cd4021bm96.lbr"
    },
    "distributor_links": {
      "digikey": "296-38905-2-ND",
      "lcsc": "C134120"
    },
    "pins": [
      {
        "number": "1",
        "name": "P1-8",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 8 (PI-8). When PARALLEL/SERIAL CONTROL is high the level on this pin is asynchronously jammed into the 8th register stage. High-impedance CMOS input; VIH >= 3.5 V at VDD=5 V, 7 V at 10 V, 11 V at 15 V."
      },
      {
        "number": "2",
        "name": "Q6",
        "type": "output",
        "description": "Buffered non-inverting parallel output of register stage 6. CMOS push-pull output; VOH >= 4.95 V at VDD=5 V, IOH typ. -1 mA. Reflects the state of the 6th stage flip-flop (updated on the rising CLOCK edge in serial mode or asynchronously in parallel mode)."
      },
      {
        "number": "3",
        "name": "Q8",
        "type": "output",
        "description": "Buffered non-inverting parallel output of register stage 8 (last stage, also used as serial-out for cascading). CMOS push-pull output; VOH >= 4.95 V at VDD=5 V, IOH typ. -1 mA."
      },
      {
        "number": "4",
        "name": "P1-4",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 4 (PI-4). Asynchronously loaded into stage 4 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "5",
        "name": "P1-3",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 3 (PI-3). Asynchronously loaded into stage 3 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "6",
        "name": "P1-2",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 2 (PI-2). Asynchronously loaded into stage 2 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "7",
        "name": "P1-1",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 1 (PI-1). Asynchronously loaded into stage 1 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference. Typically tied to 0 V. All input and output voltages are referenced to VSS."
      },
      {
        "number": "9",
        "name": "PARALLEL/SERIAL CONTROL",
        "type": "input",
        "description": "Mode-select input. When HIGH, the eight parallel P1-1..P1-8 inputs are asynchronously jammed into the register (parallel load). When LOW, data at SERIAL IN is shifted synchronously through the 8 stages on the positive edge of CLOCK. Minimum P/S pulse width (tWH): 160/80/50 ns at VDD=5/10/15 V; minimum removal time (tREM) before the next CLOCK edge: 280/140/100 ns."
      },
      {
        "number": "10",
        "name": "CLOCK",
        "type": "input",
        "description": "Shift clock input. On the positive-going transition of CLOCK the serial data at SERIAL IN is loaded into stage 1 and each stage is shifted to the next. Max clock frequency (fCL): 3 MHz at VDD=5 V, 6 MHz at 10 V, 8.5 MHz at 15 V. Minimum clock pulse width (tW): 180/80/50 ns; rise/fall time <= 15 us."
      },
      {
        "number": "11",
        "name": "SERIAL IN",
        "type": "input",
        "description": "Serial data input to stage 1. Sampled synchronously with the positive edge of CLOCK when PARALLEL/SERIAL CONTROL is low. Set-up time (ts) 120/80/60 ns at VDD=5/10/15 V; hold time 0 ns."
      },
      {
        "number": "12",
        "name": "Q7",
        "type": "output",
        "description": "Buffered non-inverting parallel output of register stage 7. CMOS push-pull output; VOH >= 4.95 V at VDD=5 V."
      },
      {
        "number": "13",
        "name": "P1-5",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 5 (PI-5). Asynchronously loaded into stage 5 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "14",
        "name": "P1-6",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 6 (PI-6). Asynchronously loaded into stage 6 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "15",
        "name": "P1-7",
        "type": "input",
        "description": "Parallel (JAM) data input for stage 7 (PI-7). Asynchronously loaded into stage 7 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply voltage. Recommended operating range 3 V to 18 V referenced to VSS; absolute maximum -0.5 V to +20 V. Quiescent supply current typ. 0.04 uA (5 uA max) at VDD=5 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/lit/ds/symlink/cd4021bm96.pdf",
        "pages": 28,
        "sha256": "92ad93f1b6237a10",
        "source_tier": "mfr"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -4.445
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
      "mark": "drawn"
    },
    "logic": {
      "family_id": "CD4021",
      "logic_family": "CD4000",
      "function_code": "4021",
      "function_class": "ShiftRegister",
      "function_name": "8-Bit Static Shift Register, Parallel-In/Serial-Out",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
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        "role": "plain",
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        "units": "mm",
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        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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        "sha256": "411739790f437305009e8103291e43de669c6b165a112f71939886d090a06cbc",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
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  "discovery_triggers": [
    "cd4021bm96"
  ],
  "discovery_pitch": "CD4021BM96 (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
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    "README.md",
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    "cd4021bm96.step",
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      "mpn": "CD4021BM96",
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    {
      "mpn": "CD4021BM96BMG4",
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    {
      "mpn": "CD4021BM96BMT",
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    {
      "mpn": "CD4021BM96BMTE4",
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    {
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    {
      "mpn": "CD4021BM96BE",
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    {
      "mpn": "CD4021BM96BEE4",
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    {
      "mpn": "CD4021BM96BF",
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    {
      "mpn": "CD4021BM96BF3A",
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    {
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  "updated_at": "2026-09-24T18:40:16.247Z"
}