CD4021BM96

{
 "schema": "adom.pads/1",
 "slug": "cd4021bm96",
 "footprint": "SOIC-16_3.9x9.9mm_P1.27mm",
 "generated_from": {
  "footprint": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c",
  "pins": "page.json:component.pins",
  "overrides": null
 },
 "pin1": {
  "pad": "1",
  "at": [
   -2.475,
   -4.445
  ],
  "corner": "top-left",
  "source": "silk-marker",
  "derived_from": "SOIC-16_3.9x9.9mm_P1.27mm@sha256:f9b5075740f7816c"
 },
 "pad_count": 16,
 "symbol_pins": [
  "1",
  "10",
  "11",
  "12",
  "13",
  "14",
  "15",
  "16",
  "2",
  "3",
  "4",
  "5",
  "6",
  "7",
  "8",
  "9"
 ],
 "paste_apertures": 0,
 "issues": [],
 "pads": [
  {
   "pad": "1",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "1",
   "name": "P1-8",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 8 (PI-8). When PARALLEL/SERIAL CONTROL is high the level on this pin is asynchronously jammed into the 8th register stage. High-impedance CMOS input; VIH >= 3.5 V at VDD=5 V, 7 V at 10 V, 11 V at 15 V.",
   "is_pin1": true,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "2",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "2",
   "name": "Q6",
   "type": "output",
   "description": "Buffered non-inverting parallel output of register stage 6. CMOS push-pull output; VOH >= 4.95 V at VDD=5 V, IOH typ. -1 mA. Reflects the state of the 6th stage flip-flop (updated on the rising CLOCK edge in serial mode or asynchronously in parallel mode).",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "3",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "3",
   "name": "Q8",
   "type": "output",
   "description": "Buffered non-inverting parallel output of register stage 8 (last stage, also used as serial-out for cascading). CMOS push-pull output; VOH >= 4.95 V at VDD=5 V, IOH typ. -1 mA.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "4",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    -0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "4",
   "name": "P1-4",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 4 (PI-4). Asynchronously loaded into stage 4 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "5",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "5",
   "name": "P1-3",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 3 (PI-3). Asynchronously loaded into stage 3 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "6",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "6",
   "name": "P1-2",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 2 (PI-2). Asynchronously loaded into stage 2 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "7",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "7",
   "name": "P1-1",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 1 (PI-1). Asynchronously loaded into stage 1 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "8",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    -2.475,
    4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "8",
   "name": "VSS",
   "type": "power_in",
   "description": "Negative supply / ground reference. Typically tied to 0 V. All input and output voltages are referenced to VSS.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "9",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "9",
   "name": "PARALLEL/SERIAL CONTROL",
   "type": "input",
   "description": "Mode-select input. When HIGH, the eight parallel P1-1..P1-8 inputs are asynchronously jammed into the register (parallel load). When LOW, data at SERIAL IN is shifted synchronously through the 8 stages on the positive edge of CLOCK. Minimum P/S pulse width (tWH): 160/80/50 ns at VDD=5/10/15 V; minimum removal time (tREM) before the next CLOCK edge: 280/140/100 ns.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "10",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "10",
   "name": "CLOCK",
   "type": "input",
   "description": "Shift clock input. On the positive-going transition of CLOCK the serial data at SERIAL IN is loaded into stage 1 and each stage is shifted to the next. Max clock frequency (fCL): 3 MHz at VDD=5 V, 6 MHz at 10 V, 8.5 MHz at 15 V. Minimum clock pulse width (tW): 180/80/50 ns; rise/fall time <= 15 us.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "11",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "11",
   "name": "SERIAL IN",
   "type": "input",
   "description": "Serial data input to stage 1. Sampled synchronously with the positive edge of CLOCK when PARALLEL/SERIAL CONTROL is low. Set-up time (ts) 120/80/60 ns at VDD=5/10/15 V; hold time 0 ns.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "12",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "12",
   "name": "Q7",
   "type": "output",
   "description": "Buffered non-inverting parallel output of register stage 7. CMOS push-pull output; VOH >= 4.95 V at VDD=5 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "13",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -0.635
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "13",
   "name": "P1-5",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 5 (PI-5). Asynchronously loaded into stage 5 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "14",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -1.905
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "14",
   "name": "P1-6",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 6 (PI-6). Asynchronously loaded into stage 6 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "15",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -3.175
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "15",
   "name": "P1-7",
   "type": "input",
   "description": "Parallel (JAM) data input for stage 7 (PI-7). Asynchronously loaded into stage 7 while PARALLEL/SERIAL CONTROL is high. High-impedance CMOS logic input.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  },
  {
   "pad": "16",
   "kind": "smd",
   "shape": "roundrect",
   "at": [
    2.475,
    -4.445
   ],
   "rot": 0.0,
   "size": [
    1.95,
    0.6
   ],
   "layers": [
    "F.Cu",
    "F.Mask",
    "F.Paste"
   ],
   "thermal": false,
   "pin": "16",
   "name": "VDD",
   "type": "power_in",
   "description": "Positive supply voltage. Recommended operating range 3 V to 18 V referenced to VSS; absolute maximum -0.5 V to +20 V. Quiescent supply current typ. 0.04 uA (5 uA max) at VDD=5 V.",
   "is_pin1": false,
   "source": {
    "geometry": "SOIC-16_3.9x9.9mm_P1.27mm.kicad_mod",
    "meaning": "page.json:component.pins",
    "correspondence": "kicad: symbol pin number == pad name"
   }
  }
 ]
}