component
CD4020BE
Public Made by Adomby adom
Texas Instruments Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 18h ago |
| viewers | 18h ago |
| cd4020be-etched.glb | 18h ago |
| cd4020be-etched.step | 18h ago |
| cd4020be-hero.glb | 18h ago |
| cd4020be-hero.overlay.json | 18h ago |
| cd4020be.glb | 18h ago |
| cd4020be.kicad_mod | 18h ago |
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| cd4020be.lbr | 18h ago |
| cd4020be.step | 18h ago |
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| README.md | 18h ago |
CD4020BE
Texas Instruments · Counters, Dividers · DIP-16
CD4020BE from Texas Instruments, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Q12 | output | Buffered counter stage 12 output. |
| 2 | Q13 | output | Buffered counter stage 13 output. |
| 3 | Q14 | output | Buffered counter stage 14 output, the last stage of the 14-stage ripple counter. |
| 4 | Q6 | output | Buffered counter stage 6 output. |
| 5 | Q5 | output | Buffered counter stage 5 output. |
| 6 | Q7 | output | Buffered counter stage 7 output. |
| 7 | Q4 | output | Buffered counter stage 4 output. |
| 8 | VSS | power_in | Ground/negative supply; all voltages are referenced to VSS. |
| 9 | Q1 | output | Buffered counter stage 1 output. |
| 10 | φ (INPUT PULSES) | input | Schmitt-trigger clock input; the counter advances one count on the negative transition of each input pulse, with unlimited rise and fall times allowed. |
| 11 | RESET | input | Asynchronous reset; a high level resets the counter to its all-zeros state. |
| 12 | Q9 | output | Buffered counter stage 9 output. |
| 13 | Q8 | output | Buffered counter stage 8 output. |
| 14 | Q10 | output | Buffered counter stage 10 output. |
| 15 | Q11 | output | Buffered counter stage 11 output. |
| 16 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | DIP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD4020BE - Footprint:
Package_DIP:DIP-16_W7.62mm - 3D model: DIP-16 (KiCad packages3D, STEP)
- 3D model files:
cd4020be-etched.step/cd4020be-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4020be.step/cd4020be.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (30 pp, sha256
7317dfacb7c3e8db, retrieved 2026-10-05, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).