component
CD4020B 14-Stage Counter
Public Made by Adomby adom
14-stage ripple-carry binary counter with a buffered clock input, 3 V to 18 V.
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page.json+167−8@@ -1,8 +1,11 @@ {+ "schema_version": 1,+ "type": "component", "slug": "cd4020",+ "title": "CD4020B 14-Stage Counter",+ "brief": "14-stage ripple-carry binary counter with a buffered clock input, 3 V to 18 V.", "version": "0.1.0",- "type": "component",- "description": "14-stage ripple-carry binary counter with a buffered clock input, 3 V to 18 V.",+ "license": "CC-BY-SA-4.0", "tags": [ "logic", "counter",@@ -12,6 +15,167 @@ "ti", "soic-16" ],+ "component": {+ "mpn": "CD4020B",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counter",+ "datasheet": "https://www.ti.com/lit/ds/symlink/cd4020b.pdf",+ "parts": {+ "symbol": "cd4020.kicad_sym",+ "footprint": "cd4020.kicad_mod",+ "model_3d": "cd4020.glb"+ },+ "distributor_links": {},+ "pins": [+ {+ "number": "1",+ "name": "Q12",+ "type": "output",+ "description": "Buffered counter output, stage 12 (divide-by-4096)."+ },+ {+ "number": "2",+ "name": "Q13",+ "type": "output",+ "description": "Buffered counter output, stage 13 (divide-by-8192)."+ },+ {+ "number": "3",+ "name": "Q14",+ "type": "output",+ "description": "Buffered counter output, stage 14 (divide-by-16384)."+ },+ {+ "number": "4",+ "name": "Q6",+ "type": "output",+ "description": "Buffered counter output, stage 6 (divide-by-64)."+ },+ {+ "number": "5",+ "name": "Q5",+ "type": "output",+ "description": "Buffered counter output, stage 5 (divide-by-32)."+ },+ {+ "number": "6",+ "name": "Q7",+ "type": "output",+ "description": "Buffered counter output, stage 7 (divide-by-128)."+ },+ {+ "number": "7",+ "name": "Q4",+ "type": "output",+ "description": "Buffered counter output, stage 4 (divide-by-16)."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground reference / negative supply (0 V)."+ },+ {+ "number": "9",+ "name": "Q1",+ "type": "output",+ "description": "Buffered counter output, stage 1 (divide-by-2). Stages 2 and 3 are internal and not brought out."+ },+ {+ "number": "10",+ "name": "CLOCK",+ "type": "input",+ "description": "Clock input. Counter advances one count on each high-to-low (negative-going) transition. Schmitt-triggered on CD4020B."+ },+ {+ "number": "11",+ "name": "RESET",+ "type": "input",+ "description": "Asynchronous master reset, active HIGH. When RESET is high all counter outputs (Q1, Q4-Q14) are forced to logic 0 regardless of the CLOCK state."+ },+ {+ "number": "12",+ "name": "Q9",+ "type": "output",+ "description": "Buffered counter output, stage 9 (divide-by-512)."+ },+ {+ "number": "13",+ "name": "Q8",+ "type": "output",+ "description": "Buffered counter output, stage 8 (divide-by-256)."+ },+ {+ "number": "14",+ "name": "Q10",+ "type": "output",+ "description": "Buffered counter output, stage 10 (divide-by-1024)."+ },+ {+ "number": "15",+ "name": "Q11",+ "type": "output",+ "description": "Buffered counter output, stage 11 (divide-by-2048)."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply, 3 V to 18 V (recommended 3 V to 15 V)."+ }+ ],+ "provenance": {+ "extractor": "ds2sf",+ "datasheet": {+ "url": "https://www.ti.com/lit/ds/symlink/cd4020b.pdf",+ "pages": 30,+ "sha256": "6c727e4dd1c8af65",+ "source_tier": "mfr"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "metadata": {+ "specs": {+ "Type": "14-stage ripple binary counter",+ "Logic family": "4000B (CMOS)",+ "Available outputs": "Q1, Q4 through Q14 (Q2, Q3 internal)",+ "Clock": "External, buffered input",+ "Supply voltage": "3 V to 18 V",+ "Operating temperature": "-55 C to 125 C"+ }+ },+ "sections": [+ "hero",+ "viewers",+ "readme",+ "breadcrumbs",+ "info"+ ],+ "discovery_triggers": [+ "binary counter",+ "frequency divider",+ "clock divider",+ "ripple counter"+ ],+ "discovery_pitch": "A 14-stage binary counter that divides an input clock down through eleven pinned-out stages for timing and dividers.",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }, "dependencies": {}, "hero": { "type": "image",@@ -27,10 +191,5 @@ "docs/cd4020-datasheet.pdf", "viewers/symbol.html", "viewers/footprint.html"- ],- "visibility": "public",- "author": {- "name": "Ray",- "email": "[email protected]"- }+ ] }