CD4019BM96

{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4019bm96",
  "title": "CD4019BM96",
  "brief": "Texas Instruments Logic Gates, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.1.0",
  "license": "CC-BY-SA-4.0",
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    "logic",
    "cd4019bm96",
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  "component": {
    "mpn": "CD4019BM96",
    "manufacturer": "Texas Instruments",
    "package": "SOIC-16",
    "pin_count": 16,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4019b",
    "parts": {
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      "footprint": "cd4019bm96.kicad_mod",
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      "model_3d_plain": "cd4019bm96.glb",
      "model_3d_step": "cd4019bm96-etched.step",
      "model_3d_step_plain": "cd4019bm96.step",
      "lbr": "cd4019bm96.lbr"
    },
    "distributor_links": {
      "lcsc": "C2878073"
    },
    "pins": [
      {
        "number": "1",
        "name": "B4",
        "type": "input",
        "description": "Channel-B data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input."
      },
      {
        "number": "2",
        "name": "A3",
        "type": "input",
        "description": "Channel-A data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input."
      },
      {
        "number": "3",
        "name": "B3",
        "type": "input",
        "description": "Channel-B data input to AND/OR select gate 3, contributing to output D3 = A3·Ka + B3·Kb; CMOS-protected input."
      },
      {
        "number": "4",
        "name": "A2",
        "type": "input",
        "description": "Channel-A data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input."
      },
      {
        "number": "5",
        "name": "B2",
        "type": "input",
        "description": "Channel-B data input to AND/OR select gate 2, contributing to output D2 = A2·Ka + B2·Kb; CMOS-protected input."
      },
      {
        "number": "6",
        "name": "A1",
        "type": "input",
        "description": "Channel-A data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input."
      },
      {
        "number": "7",
        "name": "B1",
        "type": "input",
        "description": "Channel-B data input to AND/OR select gate 1, contributing to output D1 = A1·Ka + B1·Kb; CMOS-protected input."
      },
      {
        "number": "8",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply/ground reference terminal; DC supply voltage VDD is referenced to VSS over a −0.5 V to +20 V range."
      },
      {
        "number": "9",
        "name": "Ka",
        "type": "input",
        "description": "Common control-bit input that selects channel A data (A1-A4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range."
      },
      {
        "number": "10",
        "name": "D1",
        "type": "output",
        "description": "Select-gate 1 output, D1 = A1·Ka + B1·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."
      },
      {
        "number": "11",
        "name": "D2",
        "type": "output",
        "description": "Select-gate 2 output, D2 = A2·Ka + B2·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."
      },
      {
        "number": "12",
        "name": "D3",
        "type": "output",
        "description": "Select-gate 3 output, D3 = A3·Ka + B3·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."
      },
      {
        "number": "13",
        "name": "D4",
        "type": "output",
        "description": "Select-gate 4 output, D4 = A4·Ka + B4·Kb, driven by the internal AND/OR logic with symmetrical output characteristics."
      },
      {
        "number": "14",
        "name": "Kb",
        "type": "input",
        "description": "Common control-bit input that selects channel B data (B1-B4) for all four select gates; CMOS-protected input, max input current 1 µA at 18 V over full temperature range."
      },
      {
        "number": "15",
        "name": "A4",
        "type": "input",
        "description": "Channel-A data input to AND/OR select gate 4, contributing to output D4 = A4·Ka + B4·Kb; CMOS-protected input."
      },
      {
        "number": "16",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive DC supply voltage terminal, referenced to VSS, rated −0.5 V to +20 V absolute maximum and 3 V to 18 V recommended over full package temperature range."
      }
    ],
    "provenance": {
      "extractor": "extract_pins 0.2",
      "factory_chain": {
        "factory": "2.0.0",
        "extractor": "extract_pins 0.2",
        "primary_model": "claude-sonnet-5",
        "primary_mode": "text+vision",
        "consensus_model": "claude-opus-4-8",
        "consensus": "agreed",
        "guards": "pin_guards 0.1: passed",
        "guard_notes": [
          "vision extraction: provenance cannot be text-verified; needs consensus"
        ],
        "pages_sent": 19,
        "cost_usd": 0.5687,
        "at": "2026-09-23T00:22:35"
      },
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4019b",
        "pages": 19,
        "sha256": "97c4321a9ad89a2e",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 16,
        "described": 16,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
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      "footprint": "viewers/footprint.html"
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    "models_3d": [
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
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        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
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      {
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        "sha256": "422cfbd75ef4966a4f1202355d680699928fe82e0fa378eaffede125f7a2aa44",
        "checked": "2026-10-19",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "Texas Instruments",
      "Package": "SOIC-16",
      "Category": "Logic",
      "Pins": "16"
    }
  },
  "variants": [],
  "sections": [
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  "discovery_triggers": [
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  "discovery_pitch": "CD4019BM96 (Texas Instruments) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
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    "path": "docs/hero.png"
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    "cd4019bm96.step",
    "cd4019bm96.lbr",
    "docs/hero.png",
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  "visibility": {
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  },
  "updated_at": "2026-09-24T18:39:51.442Z"
}