Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by adom_assets · KiCad file format 20240108

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	1d ago
viewers	cd40193bnsr: viewers · Ray	1d ago
cd40193bnsr-etched.glb	Publish 0.1.0 · Ray	1d ago
cd40193bnsr-etched.step	cd40193bnsr: factory component page (tier=mfr) · Ray	1d ago
cd40193bnsr-hero.glb	cd40193bnsr: hero GLB from the etched model (keeps the MPN mark) · Ray	1d ago
cd40193bnsr-hero.overlay.json	Publish 0.1.0 · Ray	1d ago
cd40193bnsr.glb	Publish 0.1.0 · Ray	1d ago
cd40193bnsr.kicad_mod	Publish 0.1.0 · Ray	1d ago
cd40193bnsr.kicad_sym	Publish 0.1.0 · Ray	1d ago
cd40193bnsr.lbr	Publish 0.1.0 · Ray	1d ago
cd40193bnsr.step	Publish 0.1.0 · Ray	1d ago
package.json	Publish 0.1.0 · Ray	1d ago
page.json	Set visibility: public · Ray	1d ago
README.md	Publish 0.1.0 · Ray	1d ago

CD40193BNSR

Texas Instruments · Logic ICs · SO-16-208mil

CD40193BNSR from Texas Instruments, in a SO-16-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	J2	input	Jam (preset) data input for the second bit, loaded asynchronously into Q2 when PRESET ENABLE is low.
2	Q2	output	Buffered counter output for the second bit.
3	Q1	output	Buffered counter output for the first bit.
4	CLOCK DOWN	input	Count-down clock input; the counter counts down one count on the positive clock edge while CLOCK UP is high.
5	CLOCK UP	input	Count-up clock input; the counter counts up one count on the positive clock edge while CLOCK DOWN is high.
6	Q3	output	Buffered counter output for the third bit.
7	Q4	output	Buffered counter output for the fourth bit.
8	VSS	power_in	Ground (negative supply) terminal; the reference for all voltage ratings.
9	J4	input	Jam (preset) data input for the fourth bit, loaded asynchronously into Q4 when PRESET ENABLE is low.
10	J3	input	Jam (preset) data input for the third bit, loaded asynchronously into Q3 when PRESET ENABLE is low.
11	PRESET ENABLE	input	Active-low asynchronous preset control that loads the J1-J4 jam inputs into the outputs when low.
12	CARRY	output	Active-low carry output, high while counting and going low one-half clock cycle after the maximum count in count-up mode; ties to CLOCK UP of the next stage.
13	BORROW	output	Active-low borrow output, high while counting and going low one-half clock cycle after the minimum count in count-down mode; ties to CLOCK DOWN of the next stage.
14	RESET	input	Master reset; a high level asynchronously clears all outputs to low.
15	J1	input	Jam (preset) data input for the first bit, loaded asynchronously into Q1 when PRESET ENABLE is low.
16	VDD	power_in	Positive supply; recommended 3 V to 18 V over the full temperature range, absolute maximum -0.5 V to +20 V.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SO-16-208mil
Category	Logic ICs
Pins	16

CAD (KiCad official)

Symbol: CD40193BNSR
Footprint: Adom_Gen:Texas_Instruments_CD40193
3D model: SO-16-208mil (KiCad packages3D, STEP)
3D model files: cd40193bnsr-etched.step / cd40193bnsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40193bnsr.step / cd40193bnsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (19 pp, sha256 457d83d9490c7bd5, retrieved 2026-10-29, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF