component

CD40193BE

Public Made by Adom

by adom

lingxingic Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd40193befactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
cd40193be / README.md
History Download
Ray Publish 0.1.0 d2d5795 8d ago

CD40193BE

lingxingic · Counters, Dividers · DIP-16

CD40193BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input D1, loaded into the counter when PL is LOW.
2 Q1 output Buffered counter output Q1.
3 Q0 output Buffered counter output Q0.
4 CPD input Count-down clock pulse input, active on a LOW-to-HIGH edge (edge-triggered).
5 CPU input Count-up clock pulse input, active on a LOW-to-HIGH edge (edge-triggered).
6 Q2 output Buffered counter output Q2.
7 Q3 output Buffered counter output Q3.
8 VSS power_in Ground supply voltage; voltages are referenced to VSS (0 V).
9 D3 input Parallel data input D3, loaded into the counter when PL is LOW.
10 D2 input Parallel data input D2, loaded into the counter when PL is LOW.
11 PL input Parallel load input, active LOW; it loads the D0 to D3 data into the counter.
12 TCU output Buffered terminal count-up (carry) output, active LOW.
13 TCD output Buffered terminal count-down (borrow) output, active LOW.
14 MR input Master reset input, asynchronous; a HIGH level resets the counter.
15 D0 input Parallel data input D0, loaded into the counter when PL is LOW.
16 VDD power_in Supply voltage pin; the recommended operating supply range is 3 V to 15 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage (absolute maximum, voltages referenced to VSS) VDD -0.5 18 V 5
input voltage (all inputs; max printed as VDD+0.5 V) VI -0.5 V all inputs 5
DC input current IIK -10 10 mA any one input 5
storage temperature Tstg -65 150 ℃ 5
soldering temperature, DIP package TL 245 ℃ 10s 5
supply voltage (recommended) VDD 3 15 V 6
ambient temperature (recommended) Tamb -40 125 ℃ in free air 6
HIGH-level input voltage, VDD=5V VIH 3.5 V 7
HIGH-level input voltage, VDD=10V VIH 7 V 7
HIGH-level input voltage, VDD=15V VIH 11 V 7
LOW-level input voltage, VDD=5V VIL 1.5 V 7
LOW-level input voltage, VDD=10V VIL 3 V 7
LOW-level input voltage, VDD=15V VIL 4 V 7
HIGH-level output voltage, VDD=5V VOH 4.95 V /IO/<1uA 7
HIGH-level output voltage, VDD=10V VOH 9.95 V /IO/<1uA 7
HIGH-level output voltage, VDD=15V VOH 14.95 V /IO/<1uA 7
LOW-level output voltage, VDD=5V VOL 0.05 V /IO/<1uA 7
LOW-level output voltage, VDD=10V VOL 0.05 V /IO/<1uA 7
LOW-level output voltage, VDD=15V VOL 0.05 V /IO/<1uA 7
HIGH-level output current, VDD=5V IOH -0.3 mA VO=4.6V 7
HIGH-level output current, VDD=5V IOH -1.15 mA VO=2.5V 7
HIGH-level output current, VDD=10V IOH -0.45 mA VO=9.5V 7
HIGH-level output current, VDD=15V IOH -1.4 mA VO=13.5V 7
LOW-level output current, VDD=5V IOL 0.29 mA VO=0.4V 7
LOW-level output current, VDD=10V IOL 0.38 mA VO=0.5V 7
LOW-level output current, VDD=15V IOL 1.2 mA VO=1.5V 7
input leakage current, VDD=15V II -4 4 uA VI=15V or GND 7
supply current, VDD=5V IDD 7.5 uA VI=5V or GND;IO=0A 7
supply current, VDD=10V IDD 15 uA VI=10V or GND;IO=0A 7
supply current, VDD=15V IDD 30 uA VI=15V or GND;IO=0A 7
maximum clock pulse frequency, VDD=5V fmax 2 MHZ 10
maximum clock pulse frequency, VDD=10V fmax 6 MHZ 10
maximum clock pulse frequency, VDD=15V fmax 7.5 MHZ 10
set-up time, VDD=5V tsu 192 ns Dn to PL 10
set-up time, VDD=10V tsu 72 ns Dn to PL 10
set-up time, VDD=15V tsu 60 ns Dn to PL 10
hold time, VDD=5V thold 12 ns Dn to PL 10
hold time, VDD=10V thold 6 ns Dn to PL 10
hold time, VDD=15V thold 6 ns Dn to PL 10
pulse width, CPU or CPD LOW minimum width, VDD=5V tW 180 ns CPU or CPD LOW; minimum width 10
pulse width, CPU or CPD LOW minimum width, VDD=10V tW 60 ns CPU or CPD LOW; minimum width 10
pulse width, CPU or CPD LOW minimum width, VDD=15V tW 42 ns CPU or CPD LOW; minimum width 10
transition time, VDD=5V tTHL, tTLH 144 ns See Figure 4 10
transition time, VDD=10V tTHL, tTLH 72 ns See Figure 4 10
transition time, VDD=15V tTHL, tTLH 48 ns See Figure 4 10
HIGH to LOW propagation delay CPU to Qn, VDD=5V tPHL 498 ns See Figure 4 8
HIGH to LOW propagation delay CPU to Qn, VDD=10V tPHL 198 ns See Figure 4 8
HIGH to LOW propagation delay CPU to Qn, VDD=15V tPHL 144 ns See Figure 4 8
LOW to HIGH propagation delay CPU to Qn, VDD=5V tPLH 408 ns See Figure 4 8
LOW to HIGH propagation delay CPU to Qn, VDD=10V tPLH 168 ns See Figure 4 8
LOW to HIGH propagation delay CPU to Qn, VDD=15V tPLH 120 ns See Figure 4 8
HIGH to LOW propagation delay CPD to Qn, VDD=5V tPHL 510 ns See Figure 4 9
HIGH to LOW propagation delay CPD to Qn, VDD=10V tPHL 204 ns See Figure 4 9
HIGH to LOW propagation delay CPD to Qn, VDD=15V tPHL 150 ns See Figure 4 9
LOW to HIGH propagation delay CPD to Qn, VDD=5V tPLH 408 ns See Figure 5 9
LOW to HIGH propagation delay CPD to Qn, VDD=10V tPLH 168 ns See Figure 5 9
LOW to HIGH propagation delay CPD to Qn, VDD=15V tPLH 120 ns See Figure 5 9

CAD (KiCad official)

  • Symbol: CD40193BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40193be-etched.step / cd40193be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40193be.step / cd40193be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 d10f7e4a9074bc7d, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF