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CD40192BM

Public Made by Adom

by adom

lingxingic Counters, Dividers, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd40192bmfactory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CD40192BM

lingxingic · Counters, Dividers · SOP-16

CD40192BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input D1, loaded into the counter when PL is LOW.
2 Q1 output Buffered counter output Q1.
3 Q0 output Buffered counter output Q0.
4 CPD input Count-down clock pulse input, positive (LOW-to-HIGH) edge-triggered.
5 CPU input Count-up clock pulse input, positive (LOW-to-HIGH) edge-triggered.
6 Q2 output Buffered counter output Q2.
7 Q3 output Buffered counter output Q3.
8 VSS power_in Ground supply voltage; all voltages are referenced to VSS (0 V).
9 D3 input Parallel data input D3, loaded into the counter when PL is LOW.
10 D2 input Parallel data input D2, loaded into the counter when PL is LOW.
11 PL input Parallel load input, active LOW; asynchronously loads D0 to D3 into the counter when LOW.
12 TCU output Buffered terminal count-up (carry) output, active LOW.
13 TCD output Buffered terminal count-down (borrow) output, active LOW.
14 MR input Master reset input, asynchronous; HIGH resets the counter.
15 D0 input Parallel data input D0, loaded into the counter when PL is LOW.
16 VDD power_in Supply voltage; recommended range 3 V to 15 V, absolute maximum 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V voltages referenced to VSS 5
input voltage VI -0.5 V all inputs; max printed as VDD+0.5 V 5
DC input current IIK -10 10 mA any one input 5
storage temperature Tstg -65 150 ℃ 5
soldering temperature (DIP) TL 245 ℃ 10s DIP 5
soldering temperature (SOP) TL 260 ℃ 10s SOP 5
supply voltage VDD 3 15 V 6
ambient temperature Tamb -40 125 ℃ in free air 6
HIGH-level input voltage VIH 3.5 V VDD=5V; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage VIH 7 V VDD=10V; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage VIH 11 V VDD=15V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 1.5 V VDD=5V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 3 V VDD=10V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 4 V VDD=15V; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 4.95 V VDD=5V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 9.95 V VDD=10V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 14.95 V VDD=15V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
LOW-level output voltage VOL 0.05 V VDD=5V; /IO/<1uA; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -0.3 mA VDD=5V; VO=4.6V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -1.15 mA VDD=5V; VO=2.5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -0.45 mA VDD=10V; VO=9.5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -1.4 mA VDD=15V; VO=13.5V; Tamb=-40℃ to +125℃ 7
LOW-level output current IOL 0.29 mA VDD=5V; VO=0.4V; Tamb=-40℃ to +125℃ 7
LOW-level output current IOL 0.38 mA VDD=10V; VO=0.5V; Tamb=-40℃ to +125℃ 7
LOW-level output current IOL 1.2 mA VDD=15V; VO=1.5V; Tamb=-40℃ to +125℃ 7
input leakage current II -4 4 uA VDD=15V; VI=15V or GND; Tamb=-40℃ to +125℃ 7
supply current IDD 7.5 uA VDD=5V; VI=5V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
supply current IDD 15 uA VDD=10V; VI=10V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
supply current IDD 30 uA VDD=15V; VI=15V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
maximum clock pulse frequency fmax 2 MHZ VDD=5V; VSS=0V; Tamb=-40℃ to +125℃ 10
maximum clock pulse frequency fmax 6 MHZ VDD=10V; VSS=0V; Tamb=-40℃ to +125℃ 10
maximum clock pulse frequency fmax 7.5 MHZ VDD=15V; VSS=0V; Tamb=-40℃ to +125℃ 10
set-up time Dn to PL tsu 192 ns VDD=5V; VSS=0V; Tamb=-40℃ to +125℃ 10
set-up time Dn to PL tsu 72 ns VDD=10V; VSS=0V; Tamb=-40℃ to +125℃ 10
set-up time Dn to PL tsu 60 ns VDD=15V; VSS=0V; Tamb=-40℃ to +125℃ 10
hold time Dn to PL thold 12 ns VDD=5V; VSS=0V; Tamb=-40℃ to +125℃ 10
hold time Dn to PL thold 6 ns VDD=10V; VSS=0V; Tamb=-40℃ to +125℃ 10
pulse width CPU or CPD LOW minimum width tW 180 ns VDD=5V; VSS=0V; Tamb=-40℃ to +125℃ 10
pulse width CPU or CPD LOW minimum width tW 60 ns VDD=10V; VSS=0V; Tamb=-40℃ to +125℃ 10
pulse width CPU or CPD LOW minimum width tW 42 ns VDD=15V; VSS=0V; Tamb=-40℃ to +125℃ 10
HIGH to LOW propagation delay CPU to Qn tPHL 498 ns VDD=5V; See Figure 4; Tamb=-40℃ to +125℃ 9
HIGH to LOW propagation delay CPU to Qn tPHL 198 ns VDD=10V; See Figure 4; Tamb=-40℃ to +125℃ 9
HIGH to LOW propagation delay CPU to Qn tPHL 144 ns VDD=15V; See Figure 4; Tamb=-40℃ to +125℃ 9
HIGH to LOW propagation delay CPD to Qn tPHL 510 ns VDD=5V; See Figure 4; Tamb=-40℃ to +125℃ 9
HIGH to LOW propagation delay CPD to Qn tPHL 204 ns VDD=10V; See Figure 4; Tamb=-40℃ to +125℃ 9
HIGH to LOW propagation delay CPD to Qn tPHL 150 ns VDD=15V; See Figure 4; Tamb=-40℃ to +125℃ 9
LOW to HIGH propagation delay CPU to Qn tPLH 408 ns VDD=5V; See Figure 4; Tamb=-40℃ to +125℃ 9
LOW to HIGH propagation delay CPU to Qn tPLH 168 ns VDD=10V; See Figure 4; Tamb=-40℃ to +125℃ 9
LOW to HIGH propagation delay CPU to Qn tPLH 120 ns VDD=15V; See Figure 4; Tamb=-40℃ to +125℃ 9
LOW to HIGH propagation delay CPD to Qn tPLH 408 ns VDD=5V; See Figure 5; Tamb=-40℃ to +125℃ 9
LOW to HIGH propagation delay CPD to Qn tPLH 168 ns VDD=10V; See Figure 5; Tamb=-40℃ to +125℃ 9
LOW to HIGH propagation delay CPD to Qn tPLH 120 ns VDD=15V; See Figure 5; Tamb=-40℃ to +125℃ 9

CAD (KiCad official)

  • Symbol: CD40192BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40192bm-etched.step / cd40192bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40192bm.step / cd40192bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 bc88b2a477c28846, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF