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CD40192BE

Public Made by Adom

by adom

lingxingic Counters, Dividers, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD40192BE

lingxingic · Counters, Dividers · DIP-16

CD40192BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 D1 input Parallel data input for the 4-bit counter, loaded when PL is LOW.
2 Q1 output Buffered counter output (bit 1 of the 4-bit count).
3 Q0 output Buffered counter output (bit 0 of the 4-bit count).
4 CPD input Count-down clock pulse input, active on LOW-to-HIGH positive-going edge.
5 CPU input Count-up clock pulse input, active on LOW-to-HIGH positive-going edge.
6 Q2 output Buffered counter output (bit 2 of the 4-bit count).
7 Q3 output Buffered counter output (bit 3 of the 4-bit count).
8 VSS power_in Ground supply voltage; voltages are referenced to VSS (0 V).
9 D3 input Parallel data input for the 4-bit counter, loaded when PL is LOW.
10 D2 input Parallel data input for the 4-bit counter, loaded when PL is LOW.
11 PL input Parallel load input, active LOW; loads D0-D3 into the counter.
12 TCU output Buffered terminal count-up (carry) output, active LOW.
13 TCD output Buffered terminal count-down (borrow) output, active LOW.
14 MR input Master reset input, asynchronous, active HIGH; resets the counter.
15 D0 input Parallel data input for the 4-bit counter, loaded when PL is LOW.
16 VDD power_in Supply voltage, 3 V to 15 V per the recommended operating conditions.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 5
input voltage VI -0.5 V all inputs 5
DC input current IIK -10 10 mA any one input 5
storage temperature Tstg -65 150 ℃ 5
soldering temperature TL 245 ℃ 10s DIP 5
supply voltage VDD 3 15 V 6
ambient temperature Tamb -40 125 ℃ in free air 6
HIGH-level input voltage VIH 3.5 V VDD=5V 7
HIGH-level input voltage VIH 7 V VDD=10V 7
HIGH-level input voltage VIH 11 V VDD=15V 7
LOW-level input voltage VIL 1.5 V VDD=5V 7
LOW-level input voltage VIL 3 V VDD=10V 7
LOW-level input voltage VIL 4 V VDD=15V 7
HIGH-level output voltage VOH 4.95 V VDD=5V; /IO/<1uA 7
HIGH-level output voltage VOH 9.95 V VDD=10V; /IO/<1uA 7
HIGH-level output voltage VOH 14.95 V VDD=15V; /IO/<1uA 7
LOW-level output voltage VOL 0.05 V VDD=5V; /IO/<1uA 7
HIGH-level output current IOH -0.3 mA VDD=5V; VO=4.6V 7
HIGH-level output current IOH -1.15 mA VDD=5V; VO=2.5V 7
HIGH-level output current IOH -0.45 mA VDD=10V; VO=9.5V 7
HIGH-level output current IOH -1.4 mA VDD=15V; VO=13.5V 7
LOW-level output current IOL 0.29 mA VDD=5V; VO=0.4V 7
LOW-level output current IOL 0.38 mA VDD=10V; VO=0.5V 7
LOW-level output current IOL 1.2 mA VDD=15V; VO=1.5V 7
input leakage current II -4 4 uA VDD=15V; VI=15V or GND 7
supply current IDD 7.5 uA VDD=5V; VI=5V or GND; IO=0A 7
supply current IDD 15 uA VDD=10V; VI=10V or GND; IO=0A 7
supply current IDD 30 uA VDD=15V; VI=15V or GND; IO=0A 7
HIGH to LOW propagation delay time CPU to Qn tPHL 498 ns VDD=5V; See Figure 4 9
HIGH to LOW propagation delay time CPU to Qn tPHL 198 ns VDD=10V; See Figure 4 9
HIGH to LOW propagation delay time CPU to Qn tPHL 144 ns VDD=15V; See Figure 4 9
HIGH to LOW propagation delay time CPD to Qn tPHL 510 ns VDD=5V; See Figure 4 9
HIGH to LOW propagation delay time CPD to Qn tPHL 204 ns VDD=10V; See Figure 4 9
HIGH to LOW propagation delay time CPD to Qn tPHL 150 ns VDD=15V; See Figure 4 9
HIGH to LOW propagation delay time MR to Qn tPHL 468 ns VDD=5V 9
HIGH to LOW propagation delay time MR to Qn tPHL 192 ns VDD=10V 9
HIGH to LOW propagation delay time MR to Qn tPHL 144 ns VDD=15V 9
HIGH to LOW propagation delay time PL to Qn tPHL 432 ns VDD=5V 9
HIGH to LOW propagation delay time PL to Qn tPHL 180 ns VDD=10V 9
HIGH to LOW propagation delay time PL to Qn tPHL 132 ns VDD=15V 9
LOW to HIGH propagation delay time CPU to Qn tPLH 408 ns VDD=5V; See Figure 4 9
LOW to HIGH propagation delay time CPU to Qn tPLH 168 ns VDD=10V; See Figure 4 9
LOW to HIGH propagation delay time CPU to Qn tPLH 120 ns VDD=15V; See Figure 4 9
LOW to HIGH propagation delay time CPD to Qn tPLH 408 ns VDD=5V; See Figure 5 9
LOW to HIGH propagation delay time CPD to Qn tPLH 168 ns VDD=10V; See Figure 5 9
LOW to HIGH propagation delay time CPD to Qn tPLH 120 ns VDD=15V; See Figure 5 9
set-up time Dn to PL tsu 192 ns VDD=5V 10
set-up time Dn to PL tsu 72 ns VDD=10V 10
set-up time Dn to PL tsu 60 ns VDD=15V 10
hold time Dn to PL thold 12 ns VDD=5V 10
hold time Dn to PL thold 6 ns VDD=10V 10
pulse width CPU or CPD LOW minimum width tW 180 ns VDD=5V; CPU or CPD LOW 10
pulse width CPU or CPD LOW minimum width tW 60 ns VDD=10V; CPU or CPD LOW 10
pulse width CPU or CPD LOW minimum width tW 42 ns VDD=15V; CPU or CPD LOW 10
maximum clock pulse frequency fmax 2 MHZ VDD=5V 10
maximum clock pulse frequency fmax 6 MHZ VDD=10V 10
maximum clock pulse frequency fmax 7.5 MHZ VDD=15V 10

CAD (KiCad official)

  • Symbol: CD40192BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40192be-etched.step / cd40192be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40192be.step / cd40192be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (15 pp, sha256 a4e25b9fe427e2c7, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF