Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Generated by kicad-footprint-generator · KiCad file format 20260206

Name	Last commit message	Last updated
docs	Publish 0.1.0 · Ray	1d ago
viewers	cd4018bm96: viewers · Ray	1d ago
cd4018bm96-etched.glb	cd4018bm96: factory component page (tier=lcsc) · Ray	1d ago
cd4018bm96-etched.step	cd4018bm96: factory component page (tier=lcsc) · Ray	1d ago
cd4018bm96-hero.glb	cd4018bm96: hero GLB from the etched model (keeps the MPN mark) · Ray	1d ago
cd4018bm96-hero.overlay.json	Publish 0.1.0 · Ray	1d ago
cd4018bm96.glb	Publish 0.1.0 · Ray	1d ago
cd4018bm96.kicad_mod	Publish 0.1.0 · Ray	1d ago
cd4018bm96.kicad_sym	Publish 0.1.0 · Ray	1d ago
cd4018bm96.lbr	Publish 0.1.0 · Ray	1d ago
cd4018bm96.step	Publish 0.1.0 · Ray	1d ago
package.json	Publish 0.1.0 · Ray	1d ago
page.json	Set visibility: public · Ray	1d ago
README.md	Initial commit: component/cd4018bm96 · Ray	1d ago

CD4018BM96

Texas Instruments · Counters, Dividers · SOIC-16

CD4018BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	DATA	input	Data input to the first Johnson-counter stage; feeding back Q̄5..Q̄1 here sets divide-by-10, 8, 6, 4 or 2.
2	JAM 1	input	Jam (preset) input for stage 1, loaded into the counter when PRESET ENABLE is high.
3	JAM 2	input	Jam (preset) input for stage 2, loaded into the counter when PRESET ENABLE is high.
4	Q̄2	output	Buffered inverted Q output of counter stage 2.
5	Q̄1	output	Buffered inverted Q output of counter stage 1.
6	Q̄3	output	Buffered inverted Q output of counter stage 3.
7	JAM 3	input	Jam (preset) input for stage 3, loaded into the counter when PRESET ENABLE is high.
8	VSS	power_in	Ground / negative supply terminal; all voltages are referenced to VSS.
9	JAM 4	input	Jam (preset) input for stage 4, loaded into the counter when PRESET ENABLE is high.
10	PRESET ENABLE	input	A high level allows the information on the JAM inputs to preset the counter.
11	Q̄4	output	Buffered inverted Q output of counter stage 4.
12	JAM 5	input	Jam (preset) input for stage 5, loaded into the counter when PRESET ENABLE is high.
13	Q̄5	output	Buffered inverted Q output of counter stage 5.
14	CLOCK	input	Clock input with Schmitt-trigger action allowing unlimited rise and fall times; counter advances one count on the positive-going transition.
15	RESET	input	A high level clears the counter to an all-zero condition.
16	VDD	power_in	Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: CD4018BM96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cd4018bm96-etched.step / cd4018bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4018bm96.step / cd4018bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (20 pp, sha256 c8693929a49778b6, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF