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CD4018BE

Public Made by Adom

by adom

Texas Instruments Counters, Dividers, PDIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
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cd4018be-etched.step cd4018be: factory component page (tier=lcsc) · Ray 7d ago
cd4018be-hero.glb cd4018be: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
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CD4018BE

Texas Instruments · Counters, Dividers · PDIP-16

CD4018BE from Texas Instruments, in a PDIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DATA input Serial data input to the first Johnson-counter stage; feed back Q5, Q4, Q3, Q2 or Q1 outputs here for divide-by-10, 8, 6, 4 or 2.
2 JAM 1 input Jam (preset) input for stage 1, loaded into the counter when PRESET ENABLE is high.
3 JAM 2 input Jam (preset) input for stage 2, loaded into the counter when PRESET ENABLE is high.
4 Q2̅ output Buffered inverted output of counter stage 2.
5 Q1̅ output Buffered inverted output of counter stage 1.
6 Q3̅ output Buffered inverted output of counter stage 3.
7 JAM 3 input Jam (preset) input for stage 3, loaded into the counter when PRESET ENABLE is high.
8 VSS power_in Ground / negative supply terminal; all voltages are referenced to VSS.
9 JAM 4 input Jam (preset) input for stage 4, loaded into the counter when PRESET ENABLE is high.
10 PRESET ENABLE input A high level allows the information on the JAM inputs to preset the counter.
11 Q4̅ output Buffered inverted output of counter stage 4.
12 JAM 5 input Jam (preset) input for stage 5, loaded into the counter when PRESET ENABLE is high.
13 Q5̅ output Buffered inverted output of counter stage 5.
14 CLOCK input Clock input with Schmitt trigger action allowing unlimited rise and fall times; the counter advances one count on the positive clock transition.
15 RESET input A high level clears the counter to an all-zero condition.
16 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD4018BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: PDIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4018be-etched.step / cd4018be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4018be.step / cd4018be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 c8693929a49778b6, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF