component

CD4017BM

Public Made by Adom

by adom

LX Others, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentotherscd4017bmfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 17d ago
viewers cd4017bm: viewers · Ray 17d ago
cd4017bm-etched.glb Publish 0.1.0 · Ray 17d ago
cd4017bm-etched.step cd4017bm: factory component page (tier=lcsc) · Ray 17d ago
cd4017bm-hero.glb cd4017bm: hero GLB from the etched model (keeps the MPN mark) · Ray 17d ago
cd4017bm-hero.overlay.json Publish 0.1.0 · Ray 17d ago
cd4017bm.glb Publish 0.1.0 · Ray 17d ago
cd4017bm.kicad_mod Publish 0.1.0 · Ray 17d ago
cd4017bm.kicad_sym Publish 0.1.0 · Ray 17d ago
cd4017bm.lbr Publish 0.1.0 · Ray 17d ago
cd4017bm.step Publish 0.1.0 · Ray 17d ago
package.json Publish 0.1.0 · Ray 17d ago
page.json Set visibility: public · Ray 17d ago
README.md Publish 0.1.0 · Ray 17d ago

CD4017BM

LX · Others · SOP-16

CD4017BM from LX, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q5 output Q5 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
2 Q1 output Q1 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9); it is LOW after a master reset.
3 Q0 output Q0 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9); it is HIGH after a master reset.
4 Q2 output Q2 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
5 Q6 output Q6 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
6 Q7 output Q7 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
7 Q3 output Q3 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
8 VSS power_in VSS is the ground reference (0 V); all voltages are referenced to VSS and the recommended VDD range is 3 V to 15 V.
9 Q8 output Q8 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
10 Q4 output Q4 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
11 Q9 output Q9 is one of the ten spike-free decoded active-HIGH counter outputs (Q0 to Q9).
12 Q5-9 output Active-LOW carry output that is LOW while the counter is in states 5 through 9, used to drive CP0 of the next counter when cascading.
13 CP1 input Active-LOW clock input that is HIGH-to-LOW edge-triggered; the counter advances on this edge only while CP0 is HIGH.
14 CP0 input Active-HIGH clock input that is LOW-to-HIGH edge-triggered; the counter advances on this edge only while CP1 is LOW.
15 MR input Master reset input; a HIGH level resets the counter to zero (Q0=Q5-9=HIGH, Q1 to Q9=LOW) independent of the clock inputs.
16 VDD power_in Positive supply pin; the recommended supply range is 3 V to 15 V referenced to VSS, and unused inputs must be tied to VDD, VSS, or another input.

Key specifications

Parameter Value
Manufacturer LX
Package SOP-16
Category Others
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 7
DC input current IIK -10 10 mA any one input 7
input voltage VI -0.5 V all inputs; printed max is VDD+0.5 V 7
storage temperature Tstg -65 150 ℃ 7
total power dissipation Ptot 500 mW SOP16; derates 8mW/K above 70℃ (note 2) 7
device dissipation per output transistor P 100 mW 7
soldering temperature TL 250 ℃ 10s, SOP 7
supply voltage VDD 3 15 V 7
ambient temperature Tamb -40 85 ℃ in free air 7
clock input frequency fCL 2.5 MHz VDD=5V 7
clock input frequency fCL 5 MHz VDD=10V 7
clock input frequency fCL 5.5 MHz VDD=15V 7
clock pulse width tw 200 ns VDD=5V 7
clock pulse width tw 90 ns VDD=10V 7
clock pulse width tw 60 ns VDD=15V 7
clock inhibit setup time ts 230 ns VDD=5V 7
clock inhibit setup time ts 100 ns VDD=10V 7
clock inhibit setup time ts 70 ns VDD=15V 7
reset pulse width tRW 260 ns VDD=5V 7
reset pulse width tRW 110 ns VDD=10V 7
reset pulse width tRW 60 ns VDD=15V 7
reset removal time trec 400 ns VDD=5V 7
reset removal time trec 280 ns VDD=10V 7
reset removal time trec 150 ns VDD=15V 7
supply current IDD 0.04 5 uA VO=-, VIN=0,5V, VDD=5V, Tamb=25℃ 8
supply current IDD 0.04 10 uA VO=-, VIN=0,10V, VDD=10V, Tamb=25℃ 8
supply current IDD 0.04 20 uA VO=-, VIN=0,15V, VDD=15V, Tamb=25℃ 8
LOW-level output current IOL 0.51 1 mA VO=0.4V, VIN=0,5V, VDD=5V, Tamb=25℃ 8
LOW-level output current IOL 1.3 2.6 mA VO=0.5V, VIN=0,10V, VDD=10V, Tamb=25℃ 8
LOW-level output current IOL 3.4 6.8 mA VO=1.5V, VIN=0,15V, VDD=15V, Tamb=25℃ 8
HIGH-level output current IOH -0.51 -1 mA VO=4.6V, VIN=0,5V, VDD=5V, Tamb=25℃ 8
HIGH-level output current IOH -1.6 -3.2 mA VO=2.5V, VIN=0,5V, VDD=5V, Tamb=25℃ 8
HIGH-level output current IOH -1.3 -2.6 mA VO=9.5V, VIN=0,10V, VDD=10V, Tamb=25℃ 8
HIGH-level output current IOH -3.4 -6.8 mA VO=13.5V, VIN=0,15V, VDD=15V, Tamb=25℃ 8
LOW-level output voltage VOL 0 0.05 V VIN=0,5V, VDD=5V, Tamb=25℃ 8
HIGH-level output voltage VOH 4.95 5 V VIN=0,5V, VDD=5V, Tamb=25℃ 8
HIGH-level output voltage VOH 9.95 10 V VIN=0,10V, VDD=10V, Tamb=25℃ 8
HIGH-level output voltage VOH 14.95 15 V VIN=0,15V, VDD=15V, Tamb=25℃ 8
LOW-level input voltage VIL 1.5 V VO=0.5,4.5, VIN=-, VDD=5V, Tamb=25℃ 8
LOW-level input voltage VIL 3 V VO=1,9, VIN=-, VDD=10V, Tamb=25℃ 8
LOW-level input voltage VIL 4 V VO=1.5,13.5, VIN=-, VDD=15V, Tamb=25℃ 8
HIGH-level input voltage VIH 3.5 V VO=0.5,4.5, VIN=-, VDD=5V, Tamb=25℃ 8
HIGH-level input voltage VIH 7 V VO=1,9, VIN=-, VDD=10V, Tamb=25℃ 8
HIGH-level input voltage VIH 11 V VO=1.5,13.5, VIN=-, VDD=15V, Tamb=25℃ 8
input leakage current II -0.1 0.1 uA VO=-, VIN=0,15V, VDD=15V, Tamb=25℃ 8
supply current IDD 5 uA VO=-, VIN=0,5V, VDD=5V, Tamb=-40℃ 8
supply current IDD 150 uA VO=-, VIN=0,5V, VDD=5V, Tamb=+85℃ 8
supply current IDD 10 uA VO=-, VIN=0,10V, VDD=10V, Tamb=-40℃ 8
supply current IDD 300 uA VO=-, VIN=0,10V, VDD=10V, Tamb=+85℃ 8
supply current IDD 20 uA VO=-, VIN=0,15V, VDD=15V, Tamb=-40℃ 8
supply current IDD 600 uA VO=-, VIN=0,15V, VDD=15V, Tamb=+85℃ 8
propagation delay time tPHL, tPLH 325 650 ns CP0, CP1 to Q0 to Q9; see Figure 7; VDD=5V 9
propagation delay time tPHL, tPLH 135 270 ns CP0, CP1 to Q0 to Q9; see Figure 7; VDD=10V 9
propagation delay time tPHL, tPLH 85 170 ns CP0, CP1 to Q0 to Q9; see Figure 7; VDD=15V 9
propagation delay time tPHL, tPLH 265 530 ns MR to Q0 to Q9; see Figure 7; VDD=5V 9
propagation delay time tPHL, tPLH 115 230 ns MR to Q0 to Q9; see Figure 7; VDD=10V 9

CAD (KiCad official)

  • Symbol: CD4017BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4017bm-etched.step / cd4017bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4017bm.step / cd4017bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LX datasheet (14 pp, sha256 76b86cf5c06d0035, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF