component
CD40175BPWR
Public Made by Adomby adom
Texas Instruments Flip Flops, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD40175BPWR
Texas Instruments · Flip Flops · TSSOP-16
CD40175BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLEAR | input | Active-low common clear input that simultaneously resets all four flip-flops (Q low, Q̅ high) when held at a low level. |
| 2 | Q1 | output | True output of flip-flop 1, updated on the positive-going clock transition. |
| 3 | Q1̅ | output | Complementary output of flip-flop 1. |
| 4 | D1 | input | Independent data input of flip-flop 1, transferred to Q1 on the positive-going clock edge. |
| 5 | D2 | input | Independent data input of flip-flop 2, transferred to Q2 on the positive-going clock edge. |
| 6 | Q2̅ | output | Complementary output of flip-flop 2. |
| 7 | Q2 | output | True output of flip-flop 2, updated on the positive-going clock transition. |
| 8 | VSS | power_in | Ground/negative supply terminal; all voltages are referenced to VSS. |
| 9 | CLOCK | input | Common clock input to all four flip-flops; data is transferred to the Q outputs on the positive-going transition. |
| 10 | Q3 | output | True output of flip-flop 3, updated on the positive-going clock transition. |
| 11 | Q3̅ | output | Complementary output of flip-flop 3. |
| 12 | D3 | input | Independent data input of flip-flop 3, transferred to Q3 on the positive-going clock edge. |
| 13 | D4 | input | Independent data input of flip-flop 4, transferred to Q4 on the positive-going clock edge. |
| 14 | Q4̅ | output | Complementary output of flip-flop 4. |
| 15 | Q4 | output | True output of flip-flop 4, updated on the positive-going clock transition. |
| 16 | VDD | power_in | Positive supply terminal; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD40175BPWR - Footprint:
Package_SO:TSSOP-16_4.4x5mm_P0.65mm - 3D model: TSSOP-16 (KiCad packages3D, STEP)
- 3D model files:
cd40175bpwr-etched.step/cd40175bpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd40175bpwr.step/cd40175bpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
74d578baf8369593, retrieved 2026-10-18, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).