component
CD40175BNSR
Public Made by Adomby adom
Texas Instruments Flip Flops, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD40175BNSR
Texas Instruments · Flip Flops · SO-16
CD40175BNSR from Texas Instruments, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLEAR | input | Active-low clear input common to all four flip-flops; a low level simultaneously resets all flip-flops (Q low, Q-bar high). |
| 2 | Q1 | output | True output of flip-flop 1, updated on the positive-going clock transition. |
| 3 | Q1̅ | output | Complementary output of flip-flop 1. |
| 4 | D1 | input | Independent data input of flip-flop 1. |
| 5 | D2 | input | Independent data input of flip-flop 2. |
| 6 | Q2̅ | output | Complementary output of flip-flop 2. |
| 7 | Q2 | output | True output of flip-flop 2, updated on the positive-going clock transition. |
| 8 | VSS | power_in | Ground reference (VSS = pin 8) for the supply voltage. |
| 9 | CLOCK | input | Clock input common to all flip-flops; data is transferred to the Q outputs on the positive-going clock transition. |
| 10 | Q3 | output | True output of flip-flop 3, updated on the positive-going clock transition. |
| 11 | Q3̅ | output | Complementary output of flip-flop 3. |
| 12 | D3 | input | Independent data input of flip-flop 3. |
| 13 | D4 | input | Independent data input of flip-flop 4. |
| 14 | Q4̅ | output | Complementary output of flip-flop 4. |
| 15 | Q4 | output | True output of flip-flop 4, updated on the positive-going clock transition. |
| 16 | VDD | power_in | Positive supply (VDD = pin 16); recommended supply range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
CAD (KiCad official)
- Symbol:
CD40175BNSR - Footprint:
Package_SO:SOIC-16_3.9x9.9mm_P1.27mm - 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files:
cd40175bnsr-etched.step/cd40175bnsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd40175bnsr.step/cd40175bnsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
74d578baf8369593, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD40175BNSR
**Texas Instruments** · Flip Flops · SO-16
CD40175BNSR from Texas Instruments, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLEAR | input | Active-low clear input common to all four flip-flops; a low level simultaneously resets all flip-flops (Q low, Q-bar high). |
| 2 | Q1 | output | True output of flip-flop 1, updated on the positive-going clock transition. |
| 3 | Q1̅ | output | Complementary output of flip-flop 1. |
| 4 | D1 | input | Independent data input of flip-flop 1. |
| 5 | D2 | input | Independent data input of flip-flop 2. |
| 6 | Q2̅ | output | Complementary output of flip-flop 2. |
| 7 | Q2 | output | True output of flip-flop 2, updated on the positive-going clock transition. |
| 8 | VSS | power_in | Ground reference (VSS = pin 8) for the supply voltage. |
| 9 | CLOCK | input | Clock input common to all flip-flops; data is transferred to the Q outputs on the positive-going clock transition. |
| 10 | Q3 | output | True output of flip-flop 3, updated on the positive-going clock transition. |
| 11 | Q3̅ | output | Complementary output of flip-flop 3. |
| 12 | D3 | input | Independent data input of flip-flop 3. |
| 13 | D4 | input | Independent data input of flip-flop 4. |
| 14 | Q4̅ | output | Complementary output of flip-flop 4. |
| 15 | Q4 | output | True output of flip-flop 4, updated on the positive-going clock transition. |
| 16 | VDD | power_in | Positive supply (VDD = pin 16); recommended supply range 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SO-16 |
| Category | Logic |
| Pins | 16 |
## CAD (KiCad official)
- Symbol: `CD40175BNSR`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SO-16 (KiCad packages3D, STEP)
- 3D model files: `cd40175bnsr-etched.step` / `cd40175bnsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd40175bnsr.step` / `cd40175bnsr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd40175b) (21 pp, sha256 `74d578baf8369593`, retrieved 2026-10-07, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd40175bnsr-datasheet.pdf)