main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers cd40175bm: viewers · Ray 7d ago
cd40175bm-etched.glb Publish 0.1.0 · Ray 7d ago
cd40175bm-etched.step cd40175bm: factory component page (tier=lcsc) · Ray 7d ago
cd40175bm-hero.glb cd40175bm: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
cd40175bm-hero.overlay.json Publish 0.1.0 · Ray 7d ago
cd40175bm.glb Publish 0.1.0 · Ray 7d ago
cd40175bm.kicad_mod Publish 0.1.0 · Ray 7d ago
cd40175bm.kicad_sym Publish 0.1.0 · Ray 7d ago
cd40175bm.lbr Publish 0.1.0 · Ray 7d ago
cd40175bm.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

CD40175BM

Texas Instruments · Flip Flops · SOIC-16

CD40175BM from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLEAR input Active-low common clear input that resets all four flip-feedback Q outputs low simultaneously when held low; input range -0.5 V to VDD+0.5 V.
2 Q1 output True output of flip-flop 1, updated on the positive-going clock transition.
3 Q1\ output Complementary output of flip-flop 1.
4 D1 input Data input of flip-flop 1; input range -0.5 V to VDD+0.5 V.
5 D2 input Data input of flip-flop 2; input range -0.5 V to VDD+0.5 V.
6 Q2\ output Complementary output of flip-flop 2.
7 Q2 output True output of flip-flop 2, updated on the positive-going clock transition.
8 VSS power_in Ground (VSS) supply terminal, reference for all voltage ratings.
9 CLOCK input Common clock input for all four flip-flops; data is transferred to Q on the positive-going transition.
10 Q3 output True output of flip-flop 3, updated on the positive-going clock transition.
11 Q3\ output Complementary output of flip-flop 3.
12 D3 input Data input of flip-flop 3; input range -0.5 V to VDD+0.5 V.
13 D4 input Data input of flip-flop 4; input range -0.5 V to VDD+0.5 V.
14 Q4\ output Complementary output of flip-flop 4.
15 Q4 output True output of flip-flop 4, updated on the positive-going clock transition.
16 VDD power_in Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD40175BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd40175bm-etched.step / cd40175bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40175bm.step / cd40175bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 74d578baf8369593, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF