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CD40175BE

Public Made by Adom

by adom

lingxingic Flip Flops, DIP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD40175BE

lingxingic · Flip Flops · DIP-16

CD40175BE from lingxingic, in a DIP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Master reset input; a LOW level forces Qn outputs LOW regardless of CP and D (function table, MR = L gives Qn = L).
2 Q1 output Buffered output of flip-flop 1, referenced to VSS and powered from VDD of 3 V to 15 V (recommended operating range).
3 Q1N output Complementary buffered output of flip-flop 1.
4 D1 input Data input of flip-flop 1, sampled on the positive-going edge of CP; input voltage is limited to -0.5 V to VDD+0.5 V (absolute maximum ratings).
5 D2 input Data input of flip-flop 2, sampled on the positive-going edge of CP; input voltage is limited to -0.5 V to VDD+0.5 V (absolute maximum ratings).
6 Q2N output Complementary buffered output of flip-flop 2.
7 Q2 output Buffered output of flip-flop 2.
8 VSS power_in Ground supply voltage; all voltages in the datasheet are referenced to VSS (0 V).
9 CP input Clock input; a positive-going transition loads D into the flip-flops, and minimum LOW pulse width and maximum clock frequency are specified in the AC characteristics.
10 Q3 output Buffered output of flip-flop 3.
11 Q3N output Complementary buffered output of flip-flop 3.
12 D3 input Data input of flip-flop 3, sampled on the positive-going edge of CP; input voltage is limited to -0.5 V to VDD+0.5 V (absolute maximum ratings).
13 D4 input Data input of flip-flop 4, sampled on the positive-going edge of CP; input voltage is limited to -0.5 V to VDD+0.5 V (absolute maximum ratings).
14 Q4N output Pin table labels this pin as 'data input' but its name is Q4N, and the block diagram and pin pairing identify it as the complementary output of flip-flop 4.
15 Q4 output Buffered output of flip-flop 4.
16 VDD power_in Supply voltage, 3 V to 15 V recommended (absolute maximum +18 V with respect to VSS).

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 5
input voltage VI -0.5 V all inputs; max printed as VDD+0.5 5
DC input current IIK -10 10 mA any one input 5
storage temperature Tstg -65 150 ℃ 5
soldering temperature TL 245 ℃ 10s, DIP 5
supply voltage VDD 3 15 V 6
ambient temperature Tamb -40 125 ℃ in free air 6
HIGH-level input voltage VIH 3.5 V VDD=5V; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage VIH 7 V VDD=10V; Tamb=-40℃ to +125℃ 7
HIGH-level input voltage VIH 11 V VDD=15V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 1.5 V VDD=5V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 3 V VDD=10V; Tamb=-40℃ to +125℃ 7
LOW-level input voltage VIL 4 V VDD=15V; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 4.95 V /IO/<1uA; VDD=5V; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 9.95 V /IO/<1uA; VDD=10V; Tamb=-40℃ to +125℃ 7
HIGH-level output voltage VOH 14.95 V /IO/<1uA; VDD=15V; Tamb=-40℃ to +125℃ 7
LOW-level output voltage VOL 0.05 V /IO/<1uA; VDD=5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -0.3 mA VDD=5V; VO=4.6V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -1.15 mA VDD=5V; VO=2.5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -0.45 mA VDD=10V; VO=9.5V; Tamb=-40℃ to +125℃ 7
HIGH-level output current IOH -1.4 mA VDD=15V; VO=13.5V; Tamb=-40℃ to +125℃ 7
LOW-level output current IOL 0.29 mA VDD=5V; VO=0.4V; Tamb=-40℃ to +125℃ 7
LOW-level output current IOL 0.38 mA VDD=10V; VO=0.5V; Tamb=-40℃ to +125℃ 7
LOW-level output current IOL 1.2 mA VDD=15V; VO=1.5V; Tamb=-40℃ to +125℃ 7
input leakage current II -4 4 uA VDD=15V; VI=15V or GND; Tamb=-40℃ to +125℃ 7
supply current IDD 7.5 uA VDD=5V; VI=5V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
supply current IDD 15 uA VDD=10V; VI=10V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
supply current IDD 30 uA VDD=15V; VI=15V or GND; IO=0A; Tamb=-40℃ to +125℃ 7
propagation delay time CP to Qn tPHL, tPLH 168 ns VDD=5V; See Figure 4; Tamb=-40℃ to +125℃ 8
propagation delay time CP to Qn tPHL, tPLH 78 ns VDD=10V; See Figure 4; Tamb=-40℃ to +125℃ 8
propagation delay time CP to Qn tPHL, tPLH 54 ns VDD=15V; See Figure 4; Tamb=-40℃ to +125℃ 8
MR to Qn HIGH to LOW propagation delay time tPHL 168 ns VDD=5V; See Figure 5; Tamb=-40℃ to +125℃ 8
MR to Qn HIGH to LOW propagation delay time tPHL 78 ns VDD=10V; See Figure 5; Tamb=-40℃ to +125℃ 8
MR to Qn HIGH to LOW propagation delay time tPHL 60 ns VDD=15V; See Figure 5; Tamb=-40℃ to +125℃ 8
transition time tTHL, tTLH 144 ns VDD=5V; See Figure 4; Tamb=-40℃ to +125℃ 8
transition time tTHL, tTLH 72 ns VDD=10V; See Figure 4; Tamb=-40℃ to +125℃ 8
transition time tTHL, tTLH 48 ns VDD=15V; See Figure 4; Tamb=-40℃ to +125℃ 8
set-up time tsu 72 ns VDD=5V; See Figure 5; Tamb=-40℃ to +125℃ 8
set-up time tsu 24 ns VDD=10V; See Figure 5; Tamb=-40℃ to +125℃ 8
set-up time tsu 18 ns VDD=15V; See Figure 5; Tamb=-40℃ to +125℃ 8
hold time thold 30 ns VDD=5V; Tamb=-40℃ to +125℃ 8
hold time thold 12 ns VDD=10V; Tamb=-40℃ to +125℃ 8
minimum clock pulse width; LOW tWCPL 108 ns VDD=5V; Tamb=-40℃ to +125℃ 8
minimum clock pulse width; LOW tWCPL 42 ns VDD=10V; Tamb=-40℃ to +125℃ 8
minimum clock pulse width; LOW tWCPL 30 ns VDD=15V; Tamb=-40℃ to +125℃ 8
minimum MR pulse width; LOW tWMRL 96 ns VDD=5V; Tamb=-40℃ to +125℃ 8
minimum MR pulse width; LOW tWMRL 36 ns VDD=10V; Tamb=-40℃ to +125℃ 8
minimum MR pulse width; LOW tWMRL 24 ns VDD=15V; Tamb=-40℃ to +125℃ 8
recovery time for MR tRMR 0 ns VDD=5V; Tamb=-40℃ to +125℃ 8
maximum clock pulse frequency fmax 4 MHZ VDD=5V; Tamb=-40℃ to +125℃ 8
maximum clock pulse frequency fmax 12 MHZ VDD=10V; Tamb=-40℃ to +125℃ 8
maximum clock pulse frequency fmax 16 MHZ VDD=15V; Tamb=-40℃ to +125℃ 8

CAD (KiCad official)

  • Symbol: CD40175BE
  • Footprint: Package_DIP:DIP-16_W7.62mm
  • 3D model: DIP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40175be-etched.step / cd40175be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40175be.step / cd40175be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (13 pp, sha256 b728c75437cd477b, retrieved 2026-10-16, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF