Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗

Loads on click. Unloads only if this page sits in the background.

Datasheet

Open in new tab ↗

Loads on click. Unloads only if this page sits in the background.

Download PDF

Contents

Pinout
Key specifications
CAD (KiCad official)
Provenance

README

markdown

CD40174BM96

Texas Instruments · Flip Flops · SOIC-16

CD40174BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLEAR	input	Active-low asynchronous clear input, common to all 6 flip-flops; forces all Q outputs low regardless of clock state; VIN range −0.5 V to VDD+0.5 V.
2	Q1	output	Non-inverting data output of flip-flop 1; updates to state of D1 on positive-going CLOCK edge; output current ±100 mA max at VDD=18 V, TA=25 °C.
3	D1	input	Data input for flip-flop 1; logic level present here is captured into Q1 on the positive-going CLOCK edge.
4	D2	input	Data input for flip-flop 2; logic level present here is captured into Q2 on the positive-going CLOCK edge.
5	Q2	output	Non-inverting data output of flip-flop 2; updates to state of D2 on positive-going CLOCK edge; output current ±100 mA max at VDD=18 V, TA=25 °C.
6	D3	input	Data input for flip-flop 3; logic level present here is captured into Q3 on the positive-going CLOCK edge.
7	Q3	output	Non-inverting data output of flip-flop 3; updates to state of D3 on positive-going CLOCK edge; output current ±100 mA max at VDD=18 V, TA=25 °C.
8	VSS	power_in	Ground supply reference (0 V); all signal voltages are referenced to VSS.
9	CLOCK	input	Common positive-edge-triggered clock input for all 6 flip-flops; maximum clock frequency 3.5 MHz at VDD=5 V, 7 MHz at VDD=10 V, 8 MHz at VDD=15 V.
10	Q4	output	Non-inverting data output of flip-flop 4; updates to state of D4 on positive-going CLOCK edge; output current ±100 mA max at VDD=18 V, TA=25 °C.
11	D4	input	Data input for flip-flop 4; logic level present here is captured into Q4 on the positive-going CLOCK edge.
12	D5	input	Data input for flip-flop 5; logic level present here is captured into Q5 on the positive-going CLOCK edge.
13	Q5	output	Non-inverting data output of flip-flop 5; updates to state of D5 on positive-going CLOCK edge; output current ±100 mA max at VDD=18 V, TA=25 °C.
14	D6	input	Data input for flip-flop 6; logic level present here is captured into Q6 on the positive-going CLOCK edge.
15	Q6	output	Non-inverting data output of flip-flop 6; updates to state of D6 on positive-going CLOCK edge; output current ±100 mA max at VDD=18 V, TA=25 °C.
16	VDD	power_in	Positive supply voltage; operating range 3 V to 18 V (absolute maximum −0.5 V to +20 V); quiescent device current 1 µA typ at 25 °C.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SOIC-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: CD40174BM96
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cd40174bm96-etched.step / cd40174bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40174bm96.step / cd40174bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (19 pp, sha256 ca2dc4be7c5d3e2a, retrieved 2026-09-29, tier: lcsc)
Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF