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CD40174BM

Public Made by Adom

by adom

lingxingic Flip Flops, SOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD40174BM

lingxingic · Flip Flops · SOP-16

CD40174BM from lingxingic, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 MR input Active-low master reset input: a LOW level forces all outputs O0 to O5 LOW, regardless of CP or Dn (the pin table labels it 'clock input', which conflicts with the function table).
2 O0 output Buffered output of flip-flop 0, following the D0 input on the rising edge of CP.
3 D0 input Data input to flip-flop 0, sampled on the rising edge of CP.
4 D1 input Data input to flip-flop 1, sampled on the rising edge of CP.
5 O1 output Buffered output of flip-flop 1, following the D1 input on the rising edge of CP.
6 D2 input Data input to flip-flop 2, sampled on the rising edge of CP.
7 O2 output Buffered output of flip-flop 2, following the D2 input on the rising edge of CP.
8 VSS power_in Ground supply voltage; all voltages are referenced to VSS (0 V).
9 CP input Clock input; data is transferred from Dn to On on the rising edge of CP.
10 O3 output Buffered output of flip-flop 3, following the D3 input on the rising edge of CP.
11 D3 input Data input to flip-flop 3, sampled on the rising edge of CP.
12 O4 output Buffered output of flip-flop 4, following the D4 input on the rising edge of CP.
13 D4 input Data input to flip-flop 4, sampled on the rising edge of CP.
14 D5 input Data input to flip-flop 5, sampled on the rising edge of CP.
15 O5 output Buffered output of flip-flop 5, following the D5 input on the rising edge of CP.
16 VDD power_in Positive supply voltage; recommended operating range is 3 V to 15 V, with an absolute maximum of 18 V.

Key specifications

Parameter Value
Manufacturer lingxingic
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply voltage VDD -0.5 18 V 5
input voltage VI -0.5 V all inputs; max printed as VDD+0.5 5
DC input current IIK -10 10 mA any one input 5
storage temperature Tstg -65 150 ℃ 5
soldering temperature TL 260 ℃ 10s, SOP 5
supply voltage VDD 3 15 V 6
ambient temperature Tamb -40 125 ℃ in free air 6
HIGH-level input voltage VIH 3.5 V Tamb=-40℃ to +125℃; VDD=5V 7
HIGH-level input voltage VIH 7 V Tamb=-40℃ to +125℃; VDD=10V 7
HIGH-level input voltage VIH 11 V Tamb=-40℃ to +125℃; VDD=15V 7
LOW-level input voltage VIL 1.5 V Tamb=-40℃ to +125℃; VDD=5V 7
LOW-level input voltage VIL 3 V Tamb=-40℃ to +125℃; VDD=10V 7
LOW-level input voltage VIL 4 V Tamb=-40℃ to +125℃; VDD=15V 7
HIGH-level output voltage VOH 4.95 V Tamb=-40℃ to +125℃; VDD=5V; /IO/<1uA 7
HIGH-level output voltage VOH 9.95 V Tamb=-40℃ to +125℃; VDD=10V; /IO/<1uA 7
HIGH-level output voltage VOH 14.95 V Tamb=-40℃ to +125℃; VDD=15V; /IO/<1uA 7
LOW-level output voltage VOL 0.05 V Tamb=-40℃ to +125℃; VDD=5V; /IO/<1uA 7
HIGH-level output current IOH -0.3 mA Tamb=-40℃ to +125℃; VDD=5V; VO=4.6V 7
HIGH-level output current IOH -1.15 mA Tamb=-40℃ to +125℃; VDD=5V; VO=2.5V 7
HIGH-level output current IOH -0.45 mA Tamb=-40℃ to +125℃; VDD=10V; VO=9.5V 7
HIGH-level output current IOH -1.4 mA Tamb=-40℃ to +125℃; VDD=15V; VO=13.5V 7
LOW-level output current IOL 0.29 mA Tamb=-40℃ to +125℃; VDD=5V; VO=0.4V 7
LOW-level output current IOL 0.38 mA Tamb=-40℃ to +125℃; VDD=10V; VO=0.5V 7
LOW-level output current IOL 1.2 mA Tamb=-40℃ to +125℃; VDD=15V; VO=1.5V 7
input leakage current II -4 4 uA Tamb=-40℃ to +125℃; VDD=15V; VI=15V or GND 7
supply current IDD 7.5 uA Tamb=-40℃ to +125℃; VDD=5V; VI=5V or GND; IO=0A 7
supply current IDD 15 uA Tamb=-40℃ to +125℃; VDD=10V; VI=10V or GND; IO=0A 7
supply current IDD 30 uA Tamb=-40℃ to +125℃; VDD=15V; VI=15V or GND; IO=0A 7
propagation delay time CP to Qn tPHL, tPLH 186 ns Tamb=-40℃ to +125℃; VDD=5V; See Figure 4 9
propagation delay time CP to Qn tPHL, tPLH 78 ns Tamb=-40℃ to +125℃; VDD=10V; See Figure 4 9
propagation delay time CP to Qn tPHL, tPLH 54 ns Tamb=-40℃ to +125℃; VDD=15V; See Figure 4 9
MR to Qn HIGH to LOW propagation delay time tPHL 210 ns Tamb=-40℃ to +125℃; VDD=5V; See Figure 5 9
MR to Qn HIGH to LOW propagation delay time tPHL 84 ns Tamb=-40℃ to +125℃; VDD=10V; See Figure 5 9
MR to Qn HIGH to LOW propagation delay time tPHL 60 ns Tamb=-40℃ to +125℃; VDD=15V; See Figure 5 9
transition time tTHL, tTLH 144 ns Tamb=-40℃ to +125℃; VDD=5V; See Figure 4 9
transition time tTHL, tTLH 72 ns Tamb=-40℃ to +125℃; VDD=10V; See Figure 4 9
transition time tTHL, tTLH 48 ns Tamb=-40℃ to +125℃; VDD=15V; See Figure 4 9
set-up time tsu 24 ns Tamb=-40℃ to +125℃; VDD=5V; See Figure 5 9
set-up time tsu 12 ns Tamb=-40℃ to +125℃; VDD=10V; See Figure 5 9
hold time thold 12 ns Tamb=-40℃ to +125℃; VDD=5V 9
hold time thold 6 ns Tamb=-40℃ to +125℃; VDD=10V 9
Minimum clock pulse width LOW tWCPL 84 ns Tamb=-40℃ to +125℃; VDD=5V 9
Minimum clock pulse width LOW tWCPL 36 ns Tamb=-40℃ to +125℃; VDD=10V 9
Minimum clock pulse width LOW tWCPL 24 ns Tamb=-40℃ to +125℃; VDD=15V 9
Minimum MR pulse width LOW tWMRL 84 ns Tamb=-40℃ to +125℃; VDD=5V 9
Minimum MR pulse width LOW tWMRL 45 ns Tamb=-40℃ to +125℃; VDD=10V 9
Minimum MR pulse width LOW tWMRL 30 ns Tamb=-40℃ to +125℃; VDD=15V 9
Recovery time for MR tRMR 54 ns Tamb=-40℃ to +125℃; VDD=5V 9
Recovery time for MR tRMR 24 ns Tamb=-40℃ to +125℃; VDD=10V 9
Recovery time for MR tRMR 18 ns Tamb=-40℃ to +125℃; VDD=15V 9
Maximum clock pulse frequency fmax 4 MHZ Tamb=-40℃ to +125℃; VDD=5V 9
Maximum clock pulse frequency fmax 12 MHZ Tamb=-40℃ to +125℃; VDD=10V 9
Maximum clock pulse frequency fmax 16 MHZ Tamb=-40℃ to +125℃; VDD=15V 9

CAD (KiCad official)

  • Symbol: CD40174BM
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40174bm-etched.step / cd40174bm-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40174bm.step / cd40174bm.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (14 pp, sha256 86578455ad90b59a, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF