Loads on click. Unloads only if this page sits in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF
Contents

README

markdown

CD4016BM96

Texas Instruments · Analog Switches, Multiplexers · SOIC-14

CD4016BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SIG A IN/OUT passive Signal input/output terminal of analog switch A; source/drain voltage must stay within VSS to VDD, with continuous current rated -10mA to 10mA (recommended) / -20mA to 20mA (absolute max).
2 SIG A OUT/IN passive Signal output/input terminal of analog switch A (opposite terminal from pin 1); source/drain voltage must stay within VSS to VDD.
3 SIG B IN/OUT passive Signal input/output terminal of analog switch B; source/drain voltage must stay within VSS to VDD, with continuous current rated -10mA to 10mA (recommended).
4 SIG B OUT/IN passive Signal output/input terminal of analog switch B (opposite terminal from pin 3); source/drain voltage must stay within VSS to VDD.
5 CONTROL B input Digital control input for switch B; high level VIHC and low level VILC set per VDD (e.g., VILC max 0.7V typ, VIHC min per VDD), with input current up to ±1µA max at 18V.
6 CONTROL C input Digital control input for switch C; high level VIHC and low level VILC set per VDD, with input current up to ±1µA max at 18V.
7 VSS power_in Negative/ground supply rail; VDD-VSS differential must be 3V to 18V (recommended) or up to 20V absolute maximum.
8 SIG C IN/OUT passive Signal input/output terminal of analog switch C; source/drain voltage must stay within VSS to VDD, with continuous current rated -10mA to 10mA (recommended).
9 SIG C OUT/IN passive Signal output/input terminal of analog switch C (opposite terminal from pin 8); source/drain voltage must stay within VSS to VDD.
10 SIG D OUT/IN passive Signal output/input terminal of analog switch D; source/drain voltage must stay within VSS to VDD, with continuous current rated -10mA to 10mA (recommended).
11 SIG D IN/OUT passive Signal input/output terminal of analog switch D (opposite terminal from pin 10); source/drain voltage must stay within VSS to VDD.
12 CONTROL D input Digital control input for switch D; high level VIHC and low level VILC set per VDD, with input current up to ±1µA max at 18V.
13 CONTROL A input Digital control input for switch A; high level VIHC and low level VILC set per VDD, with input current up to ±1µA max at 18V.
14 VDD power_in Positive supply rail, 3V to 18V (recommended) with respect to VSS, up to 20V absolute maximum.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Interface
Pins 14

CAD (KiCad official)

  • Symbol: CD4016BM96
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4016bm96-etched.step / cd4016bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4016bm96.step / cd4016bm96.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (30 pp, sha256 13485729bce46934, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-sonnet-5 (text+vision), consensus claude-opus-4-8 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF