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CD4015BM96
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Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD4015BM96++**Texas Instruments** · Shift Registers · SOIC-16++CD4015BM96 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLOCK B | input | Clock input for register B; the logic level at DATA B is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions. |+| 2 | Q4B | output | Parallel output of the fourth (last) stage of shift register B. |+| 3 | Q3A | output | Parallel output of the third stage of shift register A. |+| 4 | Q2A | output | Parallel output of the second stage of shift register A. |+| 5 | Q1A | output | Parallel output of the first stage of shift register A. |+| 6 | RESET A | input | Reset input for register A; a high level on this pin resets all four stages of register A to logic 0, with minimum reset pulse width specified over VDD. |+| 7 | DATA A | input | Serial data input for register A; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK A transition, subject to the minimum data setup time. |+| 8 | VSS | power_in | Negative supply/ground terminal to which all input and supply voltages are referenced (VDD range -0.5V to +20V relative to VSS). |+| 9 | CLOCK A | input | Clock input for register A; the logic level at DATA A is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions. |+| 10 | Q4A | output | Parallel output of the fourth (last) stage of shift register A. |+| 11 | Q3B | output | Parallel output of the third stage of shift register B. |+| 12 | Q2B | output | Parallel output of the second stage of shift register B. |+| 13 | Q1B | output | Parallel output of the first stage of shift register B. |+| 14 | RESET B | input | Reset input for register B; a high level on this pin resets all four stages of register B to logic 0, with minimum reset pulse width specified over VDD. |+| 15 | DATA B | input | Serial data input for register B; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK B transition, subject to the minimum data setup time. |+| 16 | VDD | power_in | Positive supply pin; DC supply-voltage range is -0.5V to +20V referenced to VSS, with recommended operation from 3V to 18V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD4015BM96`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SOIC-16 (KiCad packages3D, STEP)+- 3D model files: `cd4015bm96-etched.step` / `cd4015bm96-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4015bm96.step` / `cd4015bm96.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4015b) (16 pp, sha256 `1737b3cedb44d5c1`, retrieved 2026-09-24, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4015bm96-datasheet.pdf)
page.jsonadded+191@@ -0,0 +1,191 @@+{+ "slug": "cd4015bm96",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Shift Registers, SOIC-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4015bm96",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4015bm96.kicad_sym",+ "cd4015bm96.kicad_mod",+ "cd4015bm96.glb",+ "cd4015bm96.step",+ "cd4015bm96.lbr",+ "docs/hero.png",+ "docs/cd4015bm96-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "CD4015BM96",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Shift Registers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd4015b",+ "parts": {+ "symbol": "cd4015bm96.kicad_sym",+ "footprint": "cd4015bm96.kicad_mod",+ "model_3d": "cd4015bm96-etched.glb",+ "model_3d_plain": "cd4015bm96.glb",+ "model_3d_step": "cd4015bm96-etched.step",+ "model_3d_step_plain": "cd4015bm96.step",+ "lbr": "cd4015bm96.lbr"+ },+ "distributor_links": {+ "lcsc": "C2870719"+ },+ "pins": [+ {+ "number": "1",+ "name": "CLOCK B",+ "type": "input",+ "description": "Clock input for register B; the logic level at DATA B is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions."+ },+ {+ "number": "2",+ "name": "Q4B",+ "type": "output",+ "description": "Parallel output of the fourth (last) stage of shift register B."+ },+ {+ "number": "3",+ "name": "Q3A",+ "type": "output",+ "description": "Parallel output of the third stage of shift register A."+ },+ {+ "number": "4",+ "name": "Q2A",+ "type": "output",+ "description": "Parallel output of the second stage of shift register A."+ },+ {+ "number": "5",+ "name": "Q1A",+ "type": "output",+ "description": "Parallel output of the first stage of shift register A."+ },+ {+ "number": "6",+ "name": "RESET A",+ "type": "input",+ "description": "Reset input for register A; a high level on this pin resets all four stages of register A to logic 0, with minimum reset pulse width specified over VDD."+ },+ {+ "number": "7",+ "name": "DATA A",+ "type": "input",+ "description": "Serial data input for register A; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK A transition, subject to the minimum data setup time."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Negative supply/ground terminal to which all input and supply voltages are referenced (VDD range -0.5V to +20V relative to VSS)."+ },+ {+ "number": "9",+ "name": "CLOCK A",+ "type": "input",+ "description": "Clock input for register A; the logic level at DATA A is shifted one stage on each positive-going transition of this clock, with rise/fall time and pulse-width limits given in the recommended operating conditions."+ },+ {+ "number": "10",+ "name": "Q4A",+ "type": "output",+ "description": "Parallel output of the fourth (last) stage of shift register A."+ },+ {+ "number": "11",+ "name": "Q3B",+ "type": "output",+ "description": "Parallel output of the third stage of shift register B."+ },+ {+ "number": "12",+ "name": "Q2B",+ "type": "output",+ "description": "Parallel output of the second stage of shift register B."+ },+ {+ "number": "13",+ "name": "Q1B",+ "type": "output",+ "description": "Parallel output of the first stage of shift register B."+ },+ {+ "number": "14",+ "name": "RESET B",+ "type": "input",+ "description": "Reset input for register B; a high level on this pin resets all four stages of register B to logic 0, with minimum reset pulse width specified over VDD."+ },+ {+ "number": "15",+ "name": "DATA B",+ "type": "input",+ "description": "Serial data input for register B; the logic level present is transferred into the first stage and shifted on each positive-going CLOCK B transition, subject to the minimum data setup time."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply pin; DC supply-voltage range is -0.5V to +20V referenced to VSS, with recommended operation from 3V to 18V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 16,+ "cost_usd": 0.5921,+ "at": "2026-09-24T03:28:53"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4015b",+ "pages": 16,+ "sha256": "1737b3cedb44d5c1",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}