component

CD4013BMT

Public Made by Adom

by adom

Texas Instruments Flip Flops, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentlogiccd4013bmtfactory-2.0.0extractor-text

Verified CD4013BMT

by Ray · last 10 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

10 Nov 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CD4013BMT · SOIC-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 31-page datasheet
  • ✓distributor: lcsc C2677979, digikey 296-28569-2-ND, mouser 595-CD4013BMT
  • ✓family: SOIC-14_3.9x8.7mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-zmmx865h/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.20)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 31 kB, viewers/symbol.html 13 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cd4013bmt.kicad_sym✓ cd4013bmt.kicad_mod✓ cd4013bmt.step
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CD4013BMT

Texas Instruments · Flip Flops · SOIC-14

CD4013BMT from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Channel 1 output.
2 Q1̄ output Inverted channel 1 output.
3 CLOCK1 input Channel 1 clock input, data is transferred to Q on the positive-going clock edge.
4 RESET1 input Channel 1 reset, a high level resets the output independent of the clock.
5 D1 input Channel 1 data input.
6 SET1 input Channel 1 set, a high level sets the output independent of the clock.
7 VSS power_in Ground.
8 SET2 input Channel 2 set, a high level sets the output independent of the clock.
9 D2 input Channel 2 data input.
10 RESET2 input Channel 2 reset, a high level resets the output independent of the clock.
11 CLOCK2 input Channel 2 clock input, data is transferred to Q on the positive-going clock edge.
12 Q2̄ output Inverted channel 2 output.
13 Q2 output Channel 2 output.
14 VDD power_in Power supply, 3 V to 18 V recommended, absolute maximum 20 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC supply voltage VDD -0.5 20 V Voltages referenced to VSS terminal 4
Input voltage, all inputs -0.5 V Printed maximum is VDD + 0.5 V (not numeric) 4
DC input current, any one input 10 mA 4
Power dissipation PD 500 mW TA = -55°C to 100°C 4
Power dissipation PD 200 mW TA = 100°C to 125°C 4
Device dissipation per output transistor 100 mW 4
Operating temperature TA -55 125 °C 4
Storage temperature Tstg -65 150 °C 4
Supply voltage 3 18 V 4
Quiescent device current (IDDmax) IDD 1 µA VIN = 0 or 5, VDD = 5, TA = -55°C 5
Quiescent device current (IDDmax) IDD 0.02 1 µA VIN = 0 or 5, VDD = 5, TA = 25°C 5
Quiescent device current (IDDmax) IDD 30 µA VIN = 0 or 5, VDD = 5, TA = 85°C 5
Quiescent device current (IDDmax) IDD 2 µA VIN = 0 or 10, VDD = 10, TA = -55°C 5
Quiescent device current (IDDmax) IDD 0.02 2 µA VIN = 0 or 10, VDD = 10, TA = 25°C 5
Quiescent device current (IDDmax) IDD 60 µA VIN = 0 or 10, VDD = 10, TA = 85°C 5
Quiescent device current (IDDmax) IDD 4 µA VIN = 0 or 15, VDD = 15, TA = -55°C 5
Quiescent device current (IDDmax) IDD 0.02 4 µA VIN = 0 or 15, VDD = 15, TA = 25°C 5
Quiescent device current (IDDmax) IDD 120 µA VIN = 0 or 15, VDD = 15, TA = 85°C 5
Quiescent device current (IDDmax) IDD 20 µA VIN = 0 or 20, VDD = 20, TA = -55°C 5
Quiescent device current (IDDmax) IDD 0.04 20 µA VIN = 0 or 20, VDD = 20, TA = 25°C 5
Quiescent device current (IDDmax) IDD 600 µA VIN = 0 or 20, VDD = 20, TA = 85°C 5
Low-level output voltage (VOLmax) VOLmax 0 0.05 V VIN = 0 or 5, VDD = 5, TA = -55°C to 125°C 6
High-level output voltage (VOHmin) VOHmin 4.95 5 V VIN = 0 or 5, VDD = 5, TA = -55°C to 125°C 6
High-level output voltage (VOHmin) VOHmin 9.95 10 V VIN = 0 or 10, VDD = 10 V, TA = -55°C to 125°C 6
High-level output voltage (VOHmin) VOHmin 14.95 15 V VIN = 0 or 15, VDD = 15, TA = -55°C to 125°C 6
Input low voltage (VILmax) VILmax 1.5 V VO = 0.5 or 4.5, VDD = 5, TA = -55°C to 125°C 7
Input low voltage (VILmax) VILmax 3 V VO = 1 or 9, VDD = 10 V, TA = -55°C to 125°C 7
Input low voltage (VILmax) VILmax 4 V VO = 1.5 or 13.5, VDD = 15, TA = -55°C to 125°C 7
Input high voltage (VIHmin) VIHmin 3.5 V VO = 0.5 or 4.5, VDD = 5, TA = -55°C to 125°C 7
Input high voltage (VIHmin) VIHmin 7 V VO = 1 or 9, VDD = 10 V, TA = -55°C to 125°C 7
Input high voltage (VIHmin) VIHmin 11 V VO = 1.5 or 13.5, VDD = 15, TA = -55°C to 125°C 7
Input current (IINmax) IINmax -0.1 0.1 µA VIN = 0 or 18, VDD = 18, TA = -55°C 7
Input current (IINmax) IINmax -1 1 µA VIN = 0 or 18, VDD = 18, TA = 85°C 7
Output low (sink) current (IOLmin) IOLmin 0.51 1 mA VO = 0.4, VIN = 0 or 5, VDD = 5, TA = 25°C 6
Output low (sink) current (IOLmin) IOLmin 1.3 2.6 mA VO = 0.5, VIN = 0 or 10, VDD = 10, TA = 25°C 6
Output low (sink) current (IOLmin) IOLmin 3.4 6.8 mA VO = 1.5, VIN = 0 or 15, VDD = 15, TA = 25°C 6
Output high (source) current (IOHmin) IOHmin -0.51 -1 mA VO = 4.6, VIN = 0 or 5, VDD = 5, TA = 25°C 6
Output high (source) current (IOHmin) IOHmin -1.3 -2.6 mA VO = 9.5, VIN = 0 or 10, VDD = 10, TA = 25°C 6
Output high (source) current (IOHmin) IOHmin -3.4 -6.8 mA VO = 13.5, VIN = 0 or 15, VDD = 15, TA = 25°C 6
Propagation delay time, clock to Q or Q outputs tPHL, tPLH 150 300 ns VDD = 5; TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 20 kΩ 7
Propagation delay time, clock to Q or Q outputs tPHL, tPLH 65 130 ns VDD = 10; TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 20 kΩ 7
Propagation delay time, clock to Q or Q outputs tPHL, tPLH 45 90 ns VDD = 15; TA = 25°C, input tr, tf = 20 ns, CL = 50 pF, RL = 20 kΩ 7
Junction-to-ambient thermal resistance (D / SOIC 14-pin) RθJA 92.5 °C/W D (SOIC) 14-pin package 5
Junction-to-case (top) thermal resistance (D / SOIC 14-pin) RθJC(top) 54 °C/W D (SOIC) 14-pin package 5
Junction-to-board thermal resistance (D / SOIC 14-pin) RθJB 46.8 °C/W D (SOIC) 14-pin package 5

CAD (KiCad official)

  • Symbol: CD4013BMT
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: cd4013bmt-etched.step / cd4013bmt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4013bmt.step / cd4013bmt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (31 pp, sha256 426ea8a5c9f8f4d0, retrieved 2026-11-10, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF