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CD4013BDRG

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HANSCHIP semiconductor Flip Flops, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4013BDRG

HANSCHIP semiconductor · Flip Flops · SOP-14

CD4013BDRG from HANSCHIP semiconductor, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Q output Logic positive output of flip-flop 1 (non-inverted Q output).
2 ~{1Q} output Logic negative (inverted) output of flip-flop 1.
3 1CP input Clock input of flip-flop 1, active on the low-to-high rising edge.
4 1CD input Asynchronous reset input of flip-flop 1, active high.
5 1D input Data input of flip-flop 1; the logic level at D is transferred to Q on the rising clock edge.
6 1SD input Asynchronous set input of flip-flop 1, active high; set and reset operate independently of the clock.
7 VSS power_in System ground (0 V).
8 2SD input Asynchronous set input of flip-flop 2, active high; set operates independently of the clock.
9 2D input Data input of flip-flop 2; the logic level at D is transferred to Q on the rising clock edge.
10 2CD input Asynchronous reset input of flip-flop 2, active high.
11 2CP input Clock input of flip-flop 2, active on the low-to-high rising edge.
12 ~{2Q} output Logic negative (inverted) output of flip-flop 2.
13 2Q output Logic positive output of flip-flop 2 (non-inverted Q output).
14 VDD power_in System supply voltage; recommended operating range 5 V to 15 V, absolute maximum 18 V.

Key specifications

Parameter Value
Manufacturer HANSCHIP semiconductor
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 4
Input clamp current IIK -10 10 mA VI < -0.5 V or VI > VDD + 0.5 V 4
Input voltage VI -0.5 V 4
Output clamp current Iok -10 10 mA VO < -0.5 V or VO > VDD + 0.5 V 4
Input/output current II/O -10 10 mA 4
Supply current IDD 50 mA 4
Operating ambient temperature Tamb -40 85 °C 4
Storage temperature Tstg -65 150 °C 4
Soldering temperature (SOP) TL 245 °C 10 s 4
Supply voltage VDD 5 15 V 4
Input voltage Vi 0 V 4
Operating ambient temperature Tamb -40 85 °C 4
Input rise/fall rate △t/△V 3.75 ns/V VDD = 5V 4
Input rise/fall rate △t/△V 0.5 ns/V VDD = 10V 4
Input rise/fall rate △t/△V 0.08 ns/V VDD = 15V 4
Quiescent supply current (IDD MAX) IDDMAX 0.02 1 uA Tamb=25℃; VIN=0,5 V; VDD=5 V 5
Quiescent supply current (IDD MAX) IDDMAX 0.02 2 uA Tamb=25℃; VIN=0,10 V; VDD=10 V 5
Quiescent supply current (IDD MAX) IDDMAX 0.02 4 uA Tamb=25℃; VIN=0,15 V; VDD=15 V 5
Low-level output current (IOL Min) IOL 0.51 1 mA Tamb=25℃; VO=0.4 V; VIN=0,5 V; VDD=5 V 5
Low-level output current (IOL Min) IOL 1.3 2.6 mA Tamb=25℃; VO=0.5 V; VIN=0,10 V; VDD=10 V 5
Low-level output current (IOL Min) IOL 3.4 6.8 mA Tamb=25℃; VO=1.5 V; VIN=0,15 V; VDD=15 V 5
High-level output current (IOH Min) IOH -0.51 -1 mA Tamb=25℃; VO=4.6 V; VIN=0,5 V; VDD=5 V 5
High-level output current (IOH Min) IOH -1.6 -3.2 mA Tamb=25℃; VO=2.5 V; VIN=0,5 V; VDD=5 V 5
High-level output current (IOH Min) IOH -1.3 -2.6 mA Tamb=25℃; VO=9.5 V; VIN=0,10 V; VDD=10 V 5
High-level output current (IOH Min) IOH -3.4 -6.8 mA Tamb=25℃; VO=13.5 V; VIN=0,15 V; VDD=15 V 5
Low-level output voltage (VOL Max) VOL 0 0.05 V Tamb=25℃; VIN=0,5 V; VDD=5 V 5
High-level output voltage (VOH Min) VOH 4.95 5 V Tamb=25℃; VIN=0,5 V; VDD=5 V 5
High-level output voltage (VOH Min) VOH 9.95 10 V Tamb=25℃; VIN=0,10 V; VDD=10 V 5
High-level output voltage (VOH Min) VOH 14.95 15 V Tamb=25℃; VIN=0,15 V; VDD=15 V 5
Low-level input voltage (VIL Max) VIL 1.5 V Tamb=25℃; VO=0.5,4.5 V; VDD=5 V 5
Low-level input voltage (VIL Max) VIL 3 V Tamb=25℃; VO=1,9 V; VDD=10 V 5
Low-level input voltage (VIL Max) VIL 4 V Tamb=25℃; VO=1.5,13.5 V; VDD=15 V 5
High-level input voltage (VIH Min) VIH 3.5 V Tamb=25℃; VO=0.5,4.5 V; VDD=5 V 5
High-level input voltage (VIH Min) VIH 7 V Tamb=25℃; VO=1,9 V; VDD=10 V 5
High-level input voltage (VIH Min) VIH 11 V Tamb=25℃; VO=1.5,13.5 V; VDD=15 V 5
Quiescent supply current (IDD MAX) at -40°C IDD 1 uA Tamb=-40℃; VIN=0,5 V; VDD=5 V 6
Quiescent supply current (IDD MAX) at +85°C IDD 30 uA Tamb=+85℃; VIN=0,5 V; VDD=5 V 6
Quiescent supply current (IDD MAX) at -40°C IDD 2 uA Tamb=-40℃; VIN=0,10 V; VDD=10 V 6
Quiescent supply current (IDD MAX) at +85°C IDD 60 uA Tamb=+85℃; VIN=0,10 V; VDD=10 V 6
Quiescent supply current (IDD MAX) at -40°C IDD 4 uA Tamb=-40℃; VIN=0,15 V; VDD=15 V 6
Quiescent supply current (IDD MAX) at +85°C IDD 120 uA Tamb=+85℃; VIN=0,15 V; VDD=15 V 6
Clock to Q / Q-bar propagation delay tPHL,tPLH 150 300 ns VDD=5 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Clock to Q / Q-bar propagation delay tPHL,tPLH 65 130 ns VDD=10 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Clock to Q / Q-bar propagation delay tPHL,tPLH 45 90 ns VDD=15 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Maximum clock input frequency fCL 3.5 7 MHZ VDD=5 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Maximum clock input frequency fCL 8 16 MHZ VDD=10 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Maximum clock input frequency fCL 12 24 MHZ VDD=15 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum clock pulse width tW 70 140 ns VDD=5 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum clock pulse width tW 30 60 ns VDD=10 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum clock pulse width tW 20 40 ns VDD=15 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum data setup time ts 20 40 ns VDD=5 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum data setup time ts 10 20 ns VDD=10 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum data setup time ts 7 15 ns VDD=15 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Minimum data hold time tH 2 5 ns VDD=5 V; tr,tf=20 ns; CL=50pF; RL=20KΩ; Tamb=25℃ 7
Input capacitance Cin 5 7.5 pF 7

CAD (KiCad official)

  • Symbol: CD4013BDRG
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4013bdrg-etched.step / cd4013bdrg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4013bdrg.step / cd4013bdrg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HANSCHIP semiconductor datasheet (14 pp, sha256 28df9258821fc242, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF