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CD4013BD

Public Made by Adom

by adom

Sungine Flip Flops, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CD4013BD

Sungine · Flip Flops · DIP-14

CD4013BD from Sungine, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Q1 output Q output of flip-flop 1, which takes the D input level on the rising clock edge.
2 ~{Q1} output Complementary Q-bar output of flip-flop 1.
3 CLK1 input Clock input of flip-flop 1; the D input level is transferred to Q on the rising edge.
4 RST1 input Active-high reset input of flip-flop 1, independent of the clock.
5 DATA1 input Data (D) input of flip-flop 1.
6 SET1 input Active-high set input of flip-flop 1, independent of the clock.
7 VSS power_in Ground (0 V) supply pin.
8 SET2 input Active-high set input of flip-flop 2, independent of the clock.
9 DATA2 input Data (D) input of flip-flop 2.
10 RST2 input Active-high reset input of flip-flop 2, independent of the clock.
11 CLK2 input Clock input of flip-flop 2; the D input level is transferred to Q on the rising edge.
12 ~{Q2} output Complementary Q-bar output of flip-flop 2.
13 Q2 output Q output of flip-flop 2, which takes the D input level on the rising clock edge.
14 VDD power_in Positive supply pin, recommended 3 to 15 V (absolute maximum -0.5 to +18 V).

Key specifications

Parameter Value
Manufacturer Sungine
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD -0.5 18 V 2
Input voltage VIN -0.5 V -0.5 ~ VDD+0.5 V 2
Storage temperature tS -65 150 ℃ 2
Power dissipation DIP PD 700 mW DIP 2
Soldering temperature tL 260 ℃ 10 秒 2
DC supply voltage VDD 3 15 V 2
Input voltage VIN 0 V 0 ~ VDD 2
Operating temperature range -10 70 ℃ 2
Input capacitance CIN 5 7.5 pF 5
Propagation delay tPHL, tPLH 200 350 nS VDD = 5V 5
Propagation delay tPHL, tPLH 80 160 nS VDD = 10V 5
Propagation delay tPHL, tPLH 65 120 nS VDD = 15V 5
Maximum clock frequency fCL 2.5 5 MHz VDD = 5V 5
Maximum clock frequency fCL 6.2 12.5 MHz VDD = 10V 5
Maximum clock frequency fCL 7.6 15.5 MHz VDD = 15V 5

CAD (KiCad official)

  • Symbol: CD4013BD
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4013bd-etched.step / cd4013bd-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4013bd.step / cd4013bd.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Sungine datasheet (7 pp, sha256 b956723ce1679a1f, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF