# CD4012BPWR

**Texas Instruments** · Logic Gates · TSSOP-14

CD4012BPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | J | output | Buffered output of gate 1, J = NOT(A·B·C·D); sink current min 0.51 mA at VDD=5 V, 25°C. |
| 2 | A | input | Gate 1 input A, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 3 | B | input | Gate 1 input B, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 4 | C | input | Gate 1 input C, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 5 | D | input | Gate 1 input D, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 6 | NC | unconnected | No connection. |
| 7 | VSS | power_in | Ground / negative supply reference; all voltages are referenced to VSS. |
| 8 | NC | unconnected | No connection. |
| 9 | E | input | Gate 2 input E, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 10 | F | input | Gate 2 input F, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 11 | G | input | Gate 2 input G, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 12 | H | input | Gate 2 input H, buffered; input voltage range -0.5 V to VDD+0.5 V. |
| 13 | K | output | Buffered output of gate 2, K = NOT(E·F·G·H); sink current min 0.51 mA at VDD=5 V, 25°C. |
| 14 | VDD | power_in | Positive supply; recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |

## CAD (KiCad official)

- Symbol: `CD4012BPWR`
- Footprint: `Package_SO:TSSOP-14_4.4x5mm_P0.65mm`
- 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4012bpwr-etched.step` / `cd4012bpwr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4012bpwr.step` / `cd4012bpwr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/cd4012b.pdf) (23 pp, sha256 `6c17dba0a390eb11`, retrieved 2026-10-18, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cd4012bpwr-datasheet.pdf)