component
CD4012BM96
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4012BM96
Texas Instruments · Logic Gates · SOIC-14
CD4012BM96 from Texas Instruments, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | Y1 | output | NAND gate 1 output, driven by the AND-NOR/inverter stage from inputs on pins 2, 3, 4, and 5. |
| 2 | A1 | input | Input A of NAND gate 1, protected by an internal CMOS protection network against VDD/VSS. |
| 3 | B1 | input | Input B of NAND gate 1, protected by an internal CMOS protection network against VDD/VSS. |
| 4 | C1 | input | Input C of NAND gate 1, protected by an internal CMOS protection network against VDD/VSS. |
| 5 | D1 | input | Input D of NAND gate 1, protected by an internal CMOS protection network against VDD/VSS. |
| 6 | NC | unconnected | No internal connection; not used in the dual 4-input NAND function and left unbonded on this 14-lead package. |
| 7 | VSS | power_in | Negative supply / ground reference for the device, referenced in all electrical characteristic test conditions. |
| 8 | NC | unconnected | No internal connection; not used in the dual 4-input NAND function and left unbonded on this 14-lead package. |
| 9 | D2 | input | Input D of NAND gate 2, protected by an internal CMOS protection network against VDD/VSS. |
| 10 | C2 | input | Input C of NAND gate 2, protected by an internal CMOS protection network against VDD/VSS. |
| 11 | B2 | input | Input B of NAND gate 2, protected by an internal CMOS protection network against VDD/VSS. |
| 12 | A2 | input | Input A of NAND gate 2, protected by an internal CMOS protection network against VDD/VSS. |
| 13 | Y2 | output | NAND gate 2 output, driven by the AND-NOR/inverter stage from inputs on pins 9, 10, 11, and 12. |
| 14 | VDD | power_in | Positive supply pin, rated for operation from 3 V to 18 V per the static electrical characteristics table. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4012BM96 - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
cd4012bm96-etched.step/cd4012bm96-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4012bm96.step/cd4012bm96.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
46a842f6da764f38, retrieved 2026-09-29, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).