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CD4012BE

Public Made by Adom

by adom

lingxingic Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CD4012BE

lingxingic · Logic Gates · DIP-14

CD4012BE from lingxingic, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1Y output Data output of gate 1; the datasheet function table gives HIGH on this pin unless all four inputs 1A to 1D are HIGH.
2 1A input Data input A of gate 1; unused inputs must be connected to VDD, GND, or another input.
3 1B input Data input B of gate 1; unused inputs must be connected to VDD, GND, or another input.
4 1C input Data input C of gate 1; unused inputs must be connected to VDD, GND, or another input.
5 1D input Data input D of gate 1; unused inputs must be connected to VDD, GND, or another input.
6 NC unconnected No connection; leave this pin unconnected.
7 GND power_in Ground (0V) reference for all voltages; the recommended VDD range of 3V to 15V is referenced to this pin.
8 NC unconnected No connection; leave this pin unconnected.
9 2A input Data input A of gate 2; unused inputs must be connected to VDD, GND, or another input.
10 2B input Data input B of gate 2; unused inputs must be connected to VDD, GND, or another input.
11 2C input Data input C of gate 2; unused inputs must be connected to VDD, GND, or another input.
12 2D input Data input D of gate 2; unused inputs must be connected to VDD, GND, or another input.
13 2Y output Data output of gate 2; the datasheet function table gives HIGH on this pin unless all four inputs 2A to 2D are HIGH.
14 VDD power_in Supply voltage, recommended range 3V to 15V (absolute maximum +18V) referenced to GND.

Key specifications

Parameter Value
Manufacturer lingxingic
Package DIP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
supply current IDD 1 uA Tamb=25℃; VIN 0, 5 V; VDD 5 V 7
LOW-level output current IOL 0.51 1 mA Tamb=25℃; VO 0.4 V; VIN 0, 5 V; VDD 5 V 7
LOW-level output current IOL 1.3 2.6 mA Tamb=25℃; VO 0.5 V; VIN 0, 10 V; VDD 10 V 7
LOW-level output current IOL 3.4 6.8 mA Tamb=25℃; VO 1.5 V; VIN 0, 15 V; VDD 15 V 7
HIGH-level output current IOH -0.51 -1 mA Tamb=25℃; VO 4.6 V; VIN 0, 5 V; VDD 5 V 7
HIGH-level output current IOH -1.6 -3.2 mA Tamb=25℃; VO 2.5 V; VIN 0, 5 V; VDD 5 V 7
HIGH-level output current IOH -1.3 -2.6 mA Tamb=25℃; VO 9.5 V; VIN 0, 10 V; VDD 10 V 7
HIGH-level output current IOH -3.4 -6.8 mA Tamb=25℃; VO 13.5 V; VIN 0, 15 V; VDD 15 V 7
LOW-level output voltage VOL 0 0.05 V Tamb=25℃; VIN 0, 5 V; VDD 5 V 7
HIGH-level output voltage VOH 4.95 5 V Tamb=25℃; VIN 0, 5 V; VDD 5 V 7
HIGH-level output voltage VOH 9.95 10 V Tamb=25℃; VIN 0, 10 V; VDD 10 V 7
HIGH-level output voltage VOH 14.95 15 V Tamb=25℃; VIN 0, 15 V; VDD 15 V 7
LOW-level input voltage VIL 1.5 V Tamb=25℃; VO 4.5 V; VDD 5 V 7
LOW-level input voltage VIL 3 V Tamb=25℃; VO 9 V; VDD 10 V 7
LOW-level input voltage VIL 4 V Tamb=25℃; VO 13.5 V; VDD 15 V 7
HIGH-level input voltage VIH 3.5 V Tamb=25℃; VO 0.5, 4.5 V; VDD 5 V 7
HIGH-level input voltage VIH 7 V Tamb=25℃; VO 1, 9 V; VDD 10 V 8
HIGH-level input voltage VIH 11 V Tamb=25℃; VO 1.5, 13.5 V; VDD 15 V 8
input leakage current II -1 1 uA Tamb=25℃; VIN 0, 15 V; VDD 15 V 8
supply current IDD 7.5 uA Tamb=+125℃; VIN 0, 5 V; VDD 5 V 8
supply current IDD 15 uA Tamb=+125℃; VIN 0, 10 V; VDD 10 V 8
supply current IDD 30 uA Tamb=+125℃; VIN 0, 15 V; VDD 15 V 8
LOW-level output current IOL 0.36 mA Tamb=+125℃; VO 0.4 V; VIN 0, 5 V; VDD 5 V 8
LOW-level output current IOL 0.9 mA Tamb=+125℃; VO 0.5 V; VIN 0, 10 V; VDD 10 V 8
LOW-level output current IOL 2.4 mA Tamb=+125℃; VO 1.5 V; VIN 0, 15 V; VDD 15 V 8
HIGH-level output current IOH -0.36 mA Tamb=+125℃; VO 4.6 V; VIN 0, 5 V; VDD 5 V 8
HIGH-level output current IOH -1.15 mA Tamb=+125℃; VO 2.5 V; VIN 0, 5 V; VDD 5 V 8
HIGH-level output current IOH -0.9 mA Tamb=+125℃; VO 9.5 V; VIN 0, 10 V; VDD 10 V 8
HIGH-level output current IOH -2.4 mA Tamb=+125℃; VO 13.5 V; VIN 0, 15 V; VDD 15 V 8
LOW-level output voltage VOL 0.05 V Tamb=+125℃; VIN 0, 5 V; VDD 5 V 8
HIGH-level output voltage VOH 4.95 V Tamb=+125℃; VIN 0, 5 V; VDD 5 V 8
HIGH-level output voltage VOH 9.95 V Tamb=+125℃; VIN 0, 10 V; VDD 10 V 8
HIGH-level output voltage VOH 14.95 V Tamb=+125℃; VIN 0, 15 V; VDD 15 V 8
LOW-level input voltage VIL 1.5 V Tamb=+125℃; VO 4.5 V; VDD 5 V 8
LOW-level input voltage VIL 3 V Tamb=+125℃; VO 9 V; VDD 10 V 8
LOW-level input voltage VIL 4 V Tamb=+125℃; VO 13.5 V; VDD 15 V 8
HIGH-level input voltage VIH 3.5 V Tamb=+125℃; VO 0.5, 4.5 V; VDD 5 V 8
supply voltage VDD -0.5 18 V Referenced to GND 7
input voltage VI -0.5 V All inputs; upper limit printed as VDD+0.5 7
DC input current IIK -10 10 mA Any one input 7
storage temperature Tstg -65 150 ℃ - 7
total power dissipation Ptot 500 mW - 7
device dissipation per output transistor P 100 mW Per output transistor 7
supply voltage VDD 3 15 V - 7
ambient temperature Tamb -40 125 ℃ In free air 7
propagation delay time tPHL, tPLH 125 250 ns See Figure 5; VDD=5V; Tamb=25℃; tr, tf=20ns; CL=50pF; RL=200kΩ 9
propagation delay time tPHL, tPLH 60 120 ns See Figure 5; VDD=10V; Tamb=25℃; tr, tf=20ns; CL=50pF; RL=200kΩ 9
propagation delay time tPHL, tPLH 45 90 ns See Figure 5; VDD=15V; Tamb=25℃; tr, tf=20ns; CL=50pF; RL=200kΩ 9
transition time tTHL, tTLH 100 200 ns See Figure 5; VDD=5V; Tamb=25℃; tr, tf=20ns; CL=50pF; RL=200kΩ 9
transition time tTHL, tTLH 50 100 ns See Figure 5; VDD=10V; Tamb=25℃; tr, tf=20ns; CL=50pF; RL=200kΩ 9
transition time tTHL, tTLH 40 80 ns See Figure 5; VDD=15V; Tamb=25℃; tr, tf=20ns; CL=50pF; RL=200kΩ 9
input capacitance CI 5 7.5 pF Any input; Tamb=25℃ 9

CAD (KiCad official)

  • Symbol: CD4012BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd4012be-etched.step / cd4012be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4012be.step / cd4012be.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: lingxingic datasheet (14 pp, sha256 c9f47d70b7eed07e, retrieved 2026-10-15, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF