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CD4011UBPWR
Public Made by Adomby adom
Texas Instruments Logic Gates, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD4011UBPWR
Texas Instruments · Logic Gates · TSSOP-14
CD4011UBPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Input A of NAND gate 1; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V, 7.0 V at VDD=10 V, 11.0 V at VDD=15 V). |
| 2 | B | input | Input B of NAND gate 1; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V, 7.0 V at VDD=10 V, 11.0 V at VDD=15 V). |
| 3 | J | output | Output J of NAND gate 1; logic NAND of inputs A and B; V_OH min 4.95 V at VDD=5 V; I_OL max 2.4 mA at VDD=5 V. |
| 4 | K | output | Output K of NAND gate 2; logic NAND of inputs C and D; V_OH min 4.95 V at VDD=5 V; I_OL max 2.4 mA at VDD=5 V. |
| 5 | C | input | Input C of NAND gate 2; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V). |
| 6 | D | input | Input D of NAND gate 2; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V). |
| 7 | VSS | power_in | Negative supply / ground reference; 0 V; all voltages referenced to this terminal. |
| 8 | E | input | Input E of NAND gate 3; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V). |
| 9 | F | input | Input F of NAND gate 3; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V). |
| 10 | L | output | Output L of NAND gate 3; logic NAND of inputs E and F; V_OH min 4.95 V at VDD=5 V; I_OL max 2.4 mA at VDD=5 V. |
| 11 | M | output | Output M of NAND gate 4; logic NAND of inputs G and H; V_OH min 4.95 V at VDD=5 V; I_OL max 2.4 mA at VDD=5 V. |
| 12 | G | input | Input G of NAND gate 4; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V). |
| 13 | H | input | Input H of NAND gate 4; one of two inputs forming a 2-input unbuffered NAND gate (V_IH min 3.5 V at VDD=5 V). |
| 14 | VDD | power_in | Positive supply voltage; operating range 3 V to 18 V (absolute max 20 V); quiescent current 100 nA typ at VDD=18 V, 25 °C. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4011UBPWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4011ubpwr-etched.step/cd4011ubpwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4011ubpwr.step/cd4011ubpwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (20 pp, sha256
62907fabea7494c9, retrieved 2026-09-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-sonnet-4-6(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).