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cd4011ubmt: factory component page (tier=lcsc)

Ray ·e7e5cd8624 · ·parent 82983d0
1 file changed +198−8
page.json+198−8
@@ -1,13 +1,208 @@ {+  "schema_version": 1,+  "type": "component",   "slug": "cd4011ubmt",+  "title": "CD4011UBMT",+  "brief": "Texas Instruments Logic Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",   "version": "0.1.0",-  "type": "component",-  "description": "Texas Instruments Logic Gates, SOIC-14. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+  "license": "CC-BY-SA-4.0",   "tags": [     "component",     "logic",     "cd4011ubmt"   ],+  "component": {+    "mpn": "CD4011UBMT",+    "manufacturer": "Texas Instruments",+    "package": "SOIC-14",+    "pin_count": 14,+    "category": "Logic",+    "subcategory": "Logic Gates",+    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4011ub",+    "parts": {+      "symbol": "cd4011ubmt.kicad_sym",+      "footprint": "cd4011ubmt.kicad_mod",+      "model_3d": "cd4011ubmt.glb",+      "model_3d_step": "cd4011ubmt.step",+      "lbr": "cd4011ubmt.lbr"+    },+    "distributor_links": {},+    "pins": [+      {+        "number": "1",+        "name": "1A",+        "type": "input",+        "description": "Gate 1 input A. High-impedance CMOS logic input for the first 2-input NAND gate; VIH/VIL scale with VDD (typ. VDD=5 V: VIH>=3.5 V, VIL<=1.5 V). Unused inputs must be tied to VDD or VSS."+      },+      {+        "number": "2",+        "name": "1B",+        "type": "input",+        "description": "Gate 1 input B. High-impedance CMOS logic input for the first 2-input NAND gate. Combined with 1A per Y = NAND(1A,1B). Unused inputs must be tied to VDD or VSS."+      },+      {+        "number": "3",+        "name": "1Y",+        "type": "output",+        "description": "Gate 1 output. Unbuffered CMOS push-pull output; Y = NOT(1A AND 1B). Typical sink/source ~1 mA at VDD=5 V."+      },+      {+        "number": "4",+        "name": "2Y",+        "type": "output",+        "description": "Gate 2 output. Unbuffered CMOS push-pull output; Y = NOT(2A AND 2B)."+      },+      {+        "number": "5",+        "name": "2A",+        "type": "input",+        "description": "Gate 2 input A. High-impedance CMOS logic input for the second 2-input NAND gate."+      },+      {+        "number": "6",+        "name": "2B",+        "type": "input",+        "description": "Gate 2 input B. High-impedance CMOS logic input for the second 2-input NAND gate."+      },+      {+        "number": "7",+        "name": "VSS",+        "type": "power_in",+        "description": "Negative supply / ground reference for all four gates. Typically 0 V. Decoupling of VDD to VSS with 0.1 uF close to the device is recommended."+      },+      {+        "number": "8",+        "name": "3B",+        "type": "input",+        "description": "Gate 3 input B. High-impedance CMOS logic input for the third 2-input NAND gate."+      },+      {+        "number": "9",+        "name": "3A",+        "type": "input",+        "description": "Gate 3 input A. High-impedance CMOS logic input for the third 2-input NAND gate."+      },+      {+        "number": "10",+        "name": "3Y",+        "type": "output",+        "description": "Gate 3 output. Unbuffered CMOS push-pull output; Y = NOT(3A AND 3B)."+      },+      {+        "number": "11",+        "name": "4Y",+        "type": "output",+        "description": "Gate 4 output. Unbuffered CMOS push-pull output; Y = NOT(4A AND 4B)."+      },+      {+        "number": "12",+        "name": "4B",+        "type": "input",+        "description": "Gate 4 input B. High-impedance CMOS logic input for the fourth 2-input NAND gate."+      },+      {+        "number": "13",+        "name": "4A",+        "type": "input",+        "description": "Gate 4 input A. High-impedance CMOS logic input for the fourth 2-input NAND gate."+      },+      {+        "number": "14",+        "name": "VDD",+        "type": "power_in",+        "description": "Positive supply for all four gates. Operating range 3 V to 18 V (CD4000B family). Decouple to VSS with 0.1 uF placed close to the device."+      }+    ],+    "provenance": {+      "extractor": "ds2sf",+      "datasheet": {+        "url": "https://www.ti.com/cn/lit/gpn/cd4011ub",+        "pages": null,+        "sha256": "bedb07024c5e0703",+        "source_tier": "lcsc"+      },+      "cad": "KiCad official (CC-BY-SA 4.0)",+      "pins": {+        "total": 14,+        "described": 14,+        "cites_pages": true,+        "refuses_to_fabricate": true+      }+    },+    "viewers": {+      "symbol": "viewers/symbol.html",+      "footprint": "viewers/footprint.html"+    }+  },+  "metadata": {+    "specs": {+      "Manufacturer": "Texas Instruments",+      "Package": "SOIC-14",+      "Category": "Logic",+      "Pins": "14"+    }+  },+  "variants": [+    {+      "mpn": "CD4011UBMT",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTM",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTM96",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTMR",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTE",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTEE4",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTF",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTF3A",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTNSR",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTPW",+      "kind": "packaging"+    },+    {+      "mpn": "CD4011UBMTPWR",+      "kind": "packaging"+    }+  ],+  "sections": [+    "hero",+    "viewers",+    "readme",+    "breadcrumbs",+    "info"+  ],+  "discovery_triggers": [+    "cd4011ubmt"+  ],+  "discovery_pitch": "CD4011UBMT (Texas Instruments) component page with datasheet-verified CAD.",+  "author": {+    "name": "Ray",+    "email": "[email protected]"+  },   "dependencies": {},   "hero": {     "type": "image",@@ -25,10 +220,5 @@     "docs/cd4011ubmt-datasheet.pdf",     "viewers/symbol.html",     "viewers/footprint.html"-  ],-  "visibility": "public",-  "author": {-    "name": "Ray",-    "email": "[email protected]"-  }+  ] }\ No newline at end of file