main
Ray cd4011s: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) 77e5160
{
  "schema_version": 1,
  "type": "component",
  "slug": "cd4011s",
  "title": "CD4011S",
  "brief": "GR Gates, SOP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "logic",
    "cd4011s"
  ],
  "component": {
    "mpn": "CD4011S",
    "manufacturer": "GR",
    "package": "SOP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Gates",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312261746_GR-CD4011S_C19818878.pdf",
    "parts": {
      "symbol": "cd4011s.kicad_sym",
      "footprint": "cd4011s.kicad_mod",
      "model_3d": "cd4011s-etched.glb",
      "model_3d_plain": "cd4011s.glb",
      "model_3d_step": "cd4011s-etched.step",
      "model_3d_step_plain": "cd4011s.step",
      "lbr": "cd4011s.lbr"
    },
    "distributor_links": {},
    "pins": [
      {
        "number": "1",
        "name": "A1",
        "type": "input",
        "description": "Input A of NAND gate 1. CMOS logic input; VIH>=3.5V @ VDD=5V, VIL<=1.5V @ VDD=5V. Input current <= 1uA."
      },
      {
        "number": "2",
        "name": "B1",
        "type": "input",
        "description": "Input B of NAND gate 1. CMOS logic input paired with A1."
      },
      {
        "number": "3",
        "name": "Y1",
        "type": "output",
        "description": "Output of NAND gate 1: Y1 = NAND(A1, B1). VOH >= 4.95V @ VDD=5V (|IOUT|<1uA); typical sourcing -1.0mA @ Vo=4.6V, sinking 2.2mA @ Vo=0.4V."
      },
      {
        "number": "4",
        "name": "Y2",
        "type": "output",
        "description": "Output of NAND gate 2: Y2 = NAND(A2, B2). Same drive characteristics as Y1."
      },
      {
        "number": "5",
        "name": "A2",
        "type": "input",
        "description": "Input A of NAND gate 2. CMOS logic input."
      },
      {
        "number": "6",
        "name": "B2",
        "type": "input",
        "description": "Input B of NAND gate 2. CMOS logic input paired with A2."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply / ground reference (0V). Absolute maximum VDD-VSS = 18V."
      },
      {
        "number": "8",
        "name": "A3",
        "type": "input",
        "description": "Input A of NAND gate 3. CMOS logic input."
      },
      {
        "number": "9",
        "name": "B3",
        "type": "input",
        "description": "Input B of NAND gate 3. CMOS logic input paired with A3."
      },
      {
        "number": "10",
        "name": "Y3",
        "type": "output",
        "description": "Output of NAND gate 3: Y3 = NAND(A3, B3)."
      },
      {
        "number": "11",
        "name": "Y4",
        "type": "output",
        "description": "Output of NAND gate 4: Y4 = NAND(A4, B4)."
      },
      {
        "number": "12",
        "name": "A4",
        "type": "input",
        "description": "Input A of NAND gate 4. CMOS logic input."
      },
      {
        "number": "13",
        "name": "B4",
        "type": "input",
        "description": "Input B of NAND gate 4. CMOS logic input paired with A4."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply. Recommended 2.5V to 15V; absolute maximum -0.5V to +18V referenced to VSS."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312261746_GR-CD4011S_C19818878.pdf",
        "pages": 5,
        "sha256": "c6ad9d7e0313c497",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "logic": {
      "family_id": "CD4011",
      "logic_family": "CD4000",
      "function_code": "4011",
      "function_class": "Gate",
      "function_name": "Quad 2-Input NAND Gate",
      "manufacturer": "Texas Instruments",
      "is_specialty": false
    },
    "models_3d": [
      {
        "file": "cd4011s.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4011s-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          8.7,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "98d2cad4f54d585fd5a418d486198bce5bdcb35e1fbadd01bb3035205bc882f4",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "GR",
      "Package": "SOP-14",
      "Category": "Logic",
      "Pins": "14"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "cd4011s"
  ],
  "discovery_pitch": "CD4011S (GR) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4011s.kicad_sym",
    "cd4011s.kicad_mod",
    "cd4011s.glb",
    "cd4011s.step",
    "cd4011s-etched.step",
    "cd4011s.lbr",
    "docs/hero.png",
    "docs/cd4011s-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "CD4011SS",
      "kind": "packaging"
    },
    {
      "mpn": "CD4011SD",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T18:38:29.909Z"
}