component
CD4011BNSR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 2d ago |
| viewers | 2d ago |
| cd4011bnsr-etched.glb | 2d ago |
| cd4011bnsr-etched.step | 2d ago |
| cd4011bnsr-hero.glb | 1d ago |
| cd4011bnsr-hero.overlay.json | 2d ago |
| cd4011bnsr.glb | 2d ago |
| cd4011bnsr.kicad_mod | 2d ago |
| cd4011bnsr.kicad_sym | 2d ago |
| cd4011bnsr.lbr | 2d ago |
| cd4011bnsr.step | 2d ago |
| package.json | 2d ago |
| page.json | 2d ago |
| README.md | 2d ago |
CD4011BNSR
Texas Instruments · Logic Gates · SOIC-14-208mil
CD4011BNSR from Texas Instruments, in a SOIC-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gate 1 input A of the quad 2-input NAND (J = NOT(A·B)); buffered, input range -0.5V to VDD+0.5V. |
| 2 | B | input | Gate 1 input B of the quad 2-input NAND (J = NOT(A·B)); buffered, input range -0.5V to VDD+0.5V. |
| 3 | J | output | Gate 1 output J = NOT(A·B); buffered output. |
| 4 | K | output | Gate 2 output K = NOT(C·D); buffered output. |
| 5 | C | input | Gate 2 input C (K = NOT(C·D)); buffered, input range -0.5V to VDD+0.5V. |
| 6 | D | input | Gate 2 input D (K = NOT(C·D)); buffered, input range -0.5V to VDD+0.5V. |
| 7 | VSS | power_in | Ground/negative supply terminal; all voltages are referenced to VSS. |
| 8 | E | input | Gate 3 input E (L = NOT(E·F)); buffered, input range -0.5V to VDD+0.5V. |
| 9 | F | input | Gate 3 input F (L = NOT(E·F)); buffered, input range -0.5V to VDD+0.5V. |
| 10 | L | output | Gate 3 output L = NOT(E·F); buffered output. |
| 11 | M | output | Gate 4 output M = NOT(G·H); buffered output. |
| 12 | G | input | Gate 4 input G (M = NOT(G·H)); buffered, input range -0.5V to VDD+0.5V. |
| 13 | H | input | Gate 4 input H (M = NOT(G·H)); buffered, input range -0.5V to VDD+0.5V. |
| 14 | VDD | power_in | Positive supply; recommended 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-14-208mil |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4011BNSR - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14-208mil (KiCad packages3D, STEP)
- 3D model files:
cd4011bnsr-etched.step/cd4011bnsr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4011bnsr.step/cd4011bnsr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (23 pp, sha256
6c17dba0a390eb11, retrieved 2026-10-07, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).