component
CD4011BNSR
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
← Commit history
README.mdadded+50@@ -0,0 +1,50 @@+# CD4011BNSR++**Texas Instruments** · Logic Gates · SOIC-14-208mil++CD4011BNSR from Texas Instruments, in a SOIC-14-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | A | input | Gate 1 input A of the quad 2-input NAND (J = NOT(A·B)); buffered, input range -0.5V to VDD+0.5V. |+| 2 | B | input | Gate 1 input B of the quad 2-input NAND (J = NOT(A·B)); buffered, input range -0.5V to VDD+0.5V. |+| 3 | J | output | Gate 1 output J = NOT(A·B); buffered output. |+| 4 | K | output | Gate 2 output K = NOT(C·D); buffered output. |+| 5 | C | input | Gate 2 input C (K = NOT(C·D)); buffered, input range -0.5V to VDD+0.5V. |+| 6 | D | input | Gate 2 input D (K = NOT(C·D)); buffered, input range -0.5V to VDD+0.5V. |+| 7 | VSS | power_in | Ground/negative supply terminal; all voltages are referenced to VSS. |+| 8 | E | input | Gate 3 input E (L = NOT(E·F)); buffered, input range -0.5V to VDD+0.5V. |+| 9 | F | input | Gate 3 input F (L = NOT(E·F)); buffered, input range -0.5V to VDD+0.5V. |+| 10 | L | output | Gate 3 output L = NOT(E·F); buffered output. |+| 11 | M | output | Gate 4 output M = NOT(G·H); buffered output. |+| 12 | G | input | Gate 4 input G (M = NOT(G·H)); buffered, input range -0.5V to VDD+0.5V. |+| 13 | H | input | Gate 4 input H (M = NOT(G·H)); buffered, input range -0.5V to VDD+0.5V. |+| 14 | VDD | power_in | Positive supply; recommended 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SOIC-14-208mil |+| Category | Logic |+| Pins | 14 |++## CAD (KiCad official)++- Symbol: `CD4011BNSR`+- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`+- 3D model: SOIC-14-208mil (KiCad packages3D, STEP)+- 3D model files: `cd4011bnsr-etched.step` / `cd4011bnsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4011bnsr.step` / `cd4011bnsr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd4012b) (23 pp, sha256 `6c17dba0a390eb11`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd4011bnsr-datasheet.pdf)
page.jsonadded+236@@ -0,0 +1,236 @@+{+ "slug": "cd4011bnsr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Logic Gates, SOIC-14-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd4011bnsr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd4011bnsr.kicad_sym",+ "cd4011bnsr.kicad_mod",+ "cd4011bnsr.glb",+ "cd4011bnsr.step",+ "cd4011bnsr.lbr",+ "docs/hero.png",+ "docs/cd4011bnsr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd4011bnsr-hero.glb",+ "cd4011bnsr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD4011BNSR",+ "manufacturer": "Texas Instruments",+ "package": "SOIC-14-208mil",+ "pin_count": 14,+ "category": "Logic",+ "subcategory": "Logic Gates",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd4012b",+ "parts": {+ "symbol": "cd4011bnsr.kicad_sym",+ "footprint": "cd4011bnsr.kicad_mod",+ "model_3d": "cd4011bnsr-hero.glb",+ "model_3d_plain": "cd4011bnsr.glb",+ "model_3d_step": "cd4011bnsr-etched.step",+ "model_3d_step_plain": "cd4011bnsr.step",+ "lbr": "cd4011bnsr.lbr"+ },+ "distributor_links": {+ "lcsc": "C5217670",+ "digikey": "296-14085-2-ND",+ "mouser": "595-CD4011BNSR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T21:37:11Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-14085-2-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-CD4011BNSR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "A",+ "type": "input",+ "description": "Gate 1 input A of the quad 2-input NAND (J = NOT(A·B)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "2",+ "name": "B",+ "type": "input",+ "description": "Gate 1 input B of the quad 2-input NAND (J = NOT(A·B)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "3",+ "name": "J",+ "type": "output",+ "description": "Gate 1 output J = NOT(A·B); buffered output."+ },+ {+ "number": "4",+ "name": "K",+ "type": "output",+ "description": "Gate 2 output K = NOT(C·D); buffered output."+ },+ {+ "number": "5",+ "name": "C",+ "type": "input",+ "description": "Gate 2 input C (K = NOT(C·D)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "6",+ "name": "D",+ "type": "input",+ "description": "Gate 2 input D (K = NOT(C·D)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "7",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground/negative supply terminal; all voltages are referenced to VSS."+ },+ {+ "number": "8",+ "name": "E",+ "type": "input",+ "description": "Gate 3 input E (L = NOT(E·F)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "9",+ "name": "F",+ "type": "input",+ "description": "Gate 3 input F (L = NOT(E·F)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "10",+ "name": "L",+ "type": "output",+ "description": "Gate 3 output L = NOT(E·F); buffered output."+ },+ {+ "number": "11",+ "name": "M",+ "type": "output",+ "description": "Gate 4 output M = NOT(G·H); buffered output."+ },+ {+ "number": "12",+ "name": "G",+ "type": "input",+ "description": "Gate 4 input G (M = NOT(G·H)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "13",+ "name": "H",+ "type": "input",+ "description": "Gate 4 input H (M = NOT(G·H)); buffered, input range -0.5V to VDD+0.5V."+ },+ {+ "number": "14",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply; recommended 3V to 18V, absolute maximum -0.5V to +20V referenced to VSS."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet has one CD4011B terminal-assignment diagram (top view) for all 14-lead packages. The N",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 23,+ "cost_usd": 0.456,+ "at": "2026-10-07T21:36:52"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd4012b",+ "pages": 23,+ "sha256": "6c17dba0a390eb11",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 14,+ "described": 14,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd4011bnsr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3b9a775da256c8afcc28dcddfbc2eb3f266107fe61ce8446d96f2c52b6f44a70",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd4011bnsr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 8.7,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "826c344f98f2b75df00f9be1c4b5b06e66a35f4cd987faac51f56f95f0b9980a",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}