component
CD4011BM-TD
Public Made by Adomby adom
TDSEMIC Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CD4011BM-TD
TDSEMIC · Logic Gates · SOP-14
CD4011BM-TD from TDSEMIC, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I1 | input | Gate 1 input A (NAND gate 1 input, output O1). |
| 2 | I2 | input | Gate 1 input B (NAND gate 1 input, output O1). |
| 3 | O1 | output | Buffered output of NAND gate 1. |
| 4 | O2 | output | Buffered output of NAND gate 2. |
| 5 | I3 | input | Gate 2 input A (NAND gate 2 input, output O2). |
| 6 | I4 | input | Gate 2 input B (NAND gate 2 input, output O2). |
| 7 | VSS | power_in | Ground (0 V) supply pin. |
| 8 | I5 | input | Gate 3 input A (NAND gate 3 input, output O3). |
| 9 | I6 | input | Gate 3 input B (NAND gate 3 input, output O3). |
| 10 | O3 | output | Buffered output of NAND gate 3. |
| 11 | O4 | output | Buffered output of NAND gate 4. |
| 12 | I7 | input | Gate 4 input A (NAND gate 4 input, output O4). |
| 13 | I8 | input | Gate 4 input B (NAND gate 4 input, output O4). |
| 14 | VDD | power_in | Positive supply pin; absolute maximum -0.5 to 18 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TDSEMIC |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
CD4011BM-TD - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
cd4011bm-td-etched.step/cd4011bm-td-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd4011bm-td.step/cd4011bm-td.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TDSEMIC datasheet (9 pp, sha256
37f0f018a328eda7, retrieved 2026-10-09, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CD4011BM-TD
**TDSEMIC** · Logic Gates · SOP-14
CD4011BM-TD from TDSEMIC, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I1 | input | Gate 1 input A (NAND gate 1 input, output O1). |
| 2 | I2 | input | Gate 1 input B (NAND gate 1 input, output O1). |
| 3 | O1 | output | Buffered output of NAND gate 1. |
| 4 | O2 | output | Buffered output of NAND gate 2. |
| 5 | I3 | input | Gate 2 input A (NAND gate 2 input, output O2). |
| 6 | I4 | input | Gate 2 input B (NAND gate 2 input, output O2). |
| 7 | VSS | power_in | Ground (0 V) supply pin. |
| 8 | I5 | input | Gate 3 input A (NAND gate 3 input, output O3). |
| 9 | I6 | input | Gate 3 input B (NAND gate 3 input, output O3). |
| 10 | O3 | output | Buffered output of NAND gate 3. |
| 11 | O4 | output | Buffered output of NAND gate 4. |
| 12 | I7 | input | Gate 4 input A (NAND gate 4 input, output O4). |
| 13 | I8 | input | Gate 4 input B (NAND gate 4 input, output O4). |
| 14 | VDD | power_in | Positive supply pin; absolute maximum -0.5 to 18 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TDSEMIC |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
## CAD (KiCad official)
- Symbol: `CD4011BM-TD`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `cd4011bm-td-etched.step` / `cd4011bm-td-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd4011bm-td.step` / `cd4011bm-td.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [TDSEMIC datasheet](docs/cd4011bm-td-datasheet.pdf) (9 pp, sha256 `37f0f018a328eda7`, retrieved 2026-10-09, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cd4011bm-td-datasheet.pdf)