main
Ray Publish 0.1.0 62e25dd 7d ago
{
  "slug": "cd4011be",
  "version": "0.1.0",
  "type": "component",
  "description": "Texas Instruments Logic Gates, DIP-14. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.",
  "tags": [
    "component",
    "logic",
    "cd4011be",
    "factory-2.0.0",
    "extractor-text"
  ],
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "cd4011be.kicad_sym",
    "cd4011be.kicad_mod",
    "cd4011be.glb",
    "cd4011be.step",
    "cd4011be.lbr",
    "docs/hero.png",
    "docs/cd4011be-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html",
    "cd4011be-hero.glb",
    "cd4011be-hero.overlay.json",
    "cd4011be-etched.glb"
  ],
  "component": {
    "mpn": "CD4011BE",
    "manufacturer": "Texas Instruments",
    "package": "DIP-14",
    "pin_count": 14,
    "category": "Logic",
    "subcategory": "Logic Gates",
    "datasheet": "https://www.ti.com/cn/lit/gpn/cd4012b",
    "parts": {
      "symbol": "cd4011be.kicad_sym",
      "footprint": "cd4011be.kicad_mod",
      "model_3d": "cd4011be-hero.glb",
      "model_3d_plain": "cd4011be-etched.glb",
      "model_3d_step": "cd4011be-etched.step",
      "model_3d_step_plain": "cd4011be.step",
      "lbr": "cd4011be.lbr"
    },
    "distributor_links": {
      "lcsc": "C5226",
      "digikey": "296-2031-ND"
    },
    "distributor_check": {
      "checked_at": "2026-10-21T16:17:15Z",
      "source": "Component Ocean /api/assign-pns",
      "digikey": {
        "pn": "296-2031-ND",
        "status": "found"
      },
      "mouser": {
        "pn": null,
        "status": "quota"
      }
    },
    "pins": [
      {
        "number": "1",
        "name": "IN1A",
        "type": "input",
        "description": "Gate 1 input 1, CMOS-protected input that must be tied to VDD or VSS when unused (VIL max 1.5 V at 5 V, VIH min 3.5 V at 5 V)."
      },
      {
        "number": "2",
        "name": "IN1B",
        "type": "input",
        "description": "Gate 1 input 2, CMOS-protected input that must be tied to VDD or VSS when unused (input capacitance 5 pF typ)."
      },
      {
        "number": "3",
        "name": "OUT1",
        "type": "output",
        "description": "Gate 1 NAND output of inputs 1 and 2, sinking 0.51 mA min and sourcing 0.51 mA min at 5 V, 25 °C."
      },
      {
        "number": "4",
        "name": "OUT2",
        "type": "output",
        "description": "Gate 2 NAND output of inputs 5 and 6, sinking 0.51 mA min and sourcing 0.51 mA min at 5 V, 25 °C."
      },
      {
        "number": "5",
        "name": "IN2A",
        "type": "input",
        "description": "Gate 2 input 1, CMOS-protected input that must be tied to VDD or VSS when unused."
      },
      {
        "number": "6",
        "name": "IN2B",
        "type": "input",
        "description": "Gate 2 input 2, CMOS-protected input that must be tied to VDD or VSS when unused."
      },
      {
        "number": "7",
        "name": "VSS",
        "type": "power_in",
        "description": "Negative supply terminal (ground, VSS) for the device."
      },
      {
        "number": "8",
        "name": "IN3A",
        "type": "input",
        "description": "Gate 3 input 1, CMOS-protected input that must be tied to VDD or VSS when unused."
      },
      {
        "number": "9",
        "name": "IN3B",
        "type": "input",
        "description": "Gate 3 input 2, CMOS-protected input that must be tied to VDD or VSS when unused."
      },
      {
        "number": "10",
        "name": "OUT3",
        "type": "output",
        "description": "Gate 3 NAND output of inputs 8 and 9, sinking 0.51 mA min and sourcing 0.51 mA min at 5 V, 25 °C."
      },
      {
        "number": "11",
        "name": "OUT4",
        "type": "output",
        "description": "Gate 4 NAND output of inputs 12 and 13, sinking 0.51 mA min and sourcing 0.51 mA min at 5 V, 25 °C."
      },
      {
        "number": "12",
        "name": "IN4A",
        "type": "input",
        "description": "Gate 4 input 1, CMOS-protected input that must be tied to VDD or VSS when unused."
      },
      {
        "number": "13",
        "name": "IN4B",
        "type": "input",
        "description": "Gate 4 input 2, CMOS-protected input that must be tied to VDD or VSS when unused."
      },
      {
        "number": "14",
        "name": "VDD",
        "type": "power_in",
        "description": "Positive supply terminal (VDD); the datasheet's static characteristics are specified at 5 V, 10 V, 15 V and 20 V."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://www.ti.com/cn/lit/gpn/cd4012b",
        "pages": 23,
        "sha256": "46a842f6da764f38",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 14,
        "described": 14,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
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        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
        "extents_mm": [
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        "zmin_mm": -3.3,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "3dae072a95c64bee0d1e58be8e75383639f5017ab982de1749d05808a4eed058",
        "checked": "2026-10-21",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "cd4011be-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "body on z = 0, through-hole leads below",
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}