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CD4011AMS

Public Made by Adom

by adom

HGSEMI Logic Gates, QSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Datasheet

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Contents

README

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CD4011AMS

HGSEMI · Logic Gates · QSOP-16

CD4011AMS from HGSEMI, in a QSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Input 1A of NAND gate 1; unused inputs must be tied to VDD, VSS or another input.
2 1B input Input 1B of NAND gate 1; unused inputs must be tied to VDD, VSS or another input.
3 1Y output Output 1Y of NAND gate 1 (NAND of 1A and 1B).
4 2Y output Output 2Y of NAND gate 2 (NAND of 2A and 2B).
5 2A input Input 2A of NAND gate 2; unused inputs must be tied to VDD, VSS or another input.
6 2B input Input 2B of NAND gate 2; unused inputs must be tied to VDD, VSS or another input.
7 VSS power_in Ground (0 V) reference for the device.
8 NC unconnected Not internally connected.
9 NC unconnected Not internally connected.
10 3A input Input 3A of NAND gate 3; unused inputs must be tied to VDD, VSS or another input.
11 3B input Input 3B of NAND gate 3; unused inputs must be tied to VDD, VSS or another input.
12 3Y output Output 3Y of NAND gate 3 (NAND of 3A and 3B).
13 4Y output Output 4Y of NAND gate 4 (NAND of 4A and 4B).
14 4A input Input 4A of NAND gate 4; unused inputs must be tied to VDD, VSS or another input.
15 4B input Input 4B of NAND gate 4; unused inputs must be tied to VDD, VSS or another input.
16 VDD power_in Positive supply voltage; the recommended range is 3 V to 13 V with VDD up to VSS+15 V absolute maximum.

Key specifications

Parameter Value
Manufacturer HGSEMI
Package QSOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (referenced to VSS) VDD -0.5 15 V Referenced to VSS pin 4
Input voltage (all inputs) VIN -0.5 V Upper limit printed as VDD+0.5 V 4
Input current (any input) IIN -10 10 mA Any one input 4
Operating temperature TA -40 85 ℃ 4
Maximum operating junction temperature TJ 150 ℃ 4
Storage temperature TS -65 150 ℃ 4
Soldering temperature TW 260 ℃ 10 s 4
Supply voltage VDD 3 13 V VSS=0 V, Tamb=25℃ unless otherwise specified 4
Input voltage VIN 0 V Maximum printed as VDD 4
Static current IDD 0 0.01 0.25 uA VI=0,5 V; VDD=5 V 5
Static current IDD 0 0.01 0.5 uA VI=0,10 V; VDD=10 V 5
Static current IDD 0 0.01 1 uA VI=0,13 V; VDD=13 V 5
Low-level output current IOL 0.51 0.88 mA VO=0.4 V; VI=0,5 V; VDD=5 V 5
Low-level output current IOL 1.3 2.25 mA VO=0.5 V; VI=0,10 V; VDD=10 V 5
Low-level output current IOL 3.4 8.8 mA VO=1.5 V; VI=0,15 V; VDD=13 V (as printed) 5
High-level output current IOH -0.51 -0.88 mA VO=4.6 V; VI=0,5 V; VDD=5 V 5
High-level output current IOH -1.3 -2.25 mA VO=9.5 V; VI=0,10 V; VDD=10 V 5
High-level output current IOH -3.4 -8.8 mA VO=11.5 V; VI=0,13 V; VDD=13 V 5
Low-level output voltage VOL 0 0.05 V VI=0,5 V; VDD=5 V 5
High-level output voltage VOH 4.95 5 V VI=0,5 V; VDD=5 V 5
High-level output voltage VOH 9.95 10 V VI=0,10 V; VDD=10 V 5
High-level output voltage VOH 12.95 13 V VI=0,13 V; VDD=13 V 5
Low-level input voltage VIL 0 1.5 V VO=0.5,4.5 V; VDD=5 V 5
Low-level input voltage VIL 0 3 V VO=1,9 V; VDD=10 V 5
Low-level input voltage VIL 0 3.5 V VO=1.5,11.5 V; VDD=13 V 5
High-level input voltage VIH 3.5 5 V VO=0.5 V; VDD=5 V 5
High-level input voltage VIH 7 10 V VO=1 V; VDD=10 V 5
High-level input voltage VIH 10 13 V VO=1.5 V; VDD=13 V 5
Propagation delay (input to output) tPHL, tPLH 120 250 ns Ref. Fig.2; VDD=5 V; tr/tf=20 ns; CL=50 pF; RL=200 kΩ; Tamb=25℃ 5
Propagation delay (input to output) tPHL, tPLH 50 100 ns Ref. Fig.2; VDD=10 V; tr/tf=20 ns; CL=50 pF; RL=200 kΩ; Tamb=25℃ 5
Propagation delay (input to output) tPHL, tPLH 35 70 ns Ref. Fig.2; VDD=13 V; tr/tf=20 ns; CL=50 pF; RL=200 kΩ; Tamb=25℃ 5
Output transition time tTHL, tTLH 90 200 ns Ref. Fig.2; VDD=5 V; tr/tf=20 ns; CL=50 pF; RL=200 kΩ; Tamb=25℃ 5
Output transition time tTHL, tTLH 50 100 ns Ref. Fig.2; VDD=10 V; tr/tf=20 ns; CL=50 pF; RL=200 kΩ; Tamb=25℃ 5
Output transition time tTHL, tTLH 40 80 ns Ref. Fig.2; VDD=13 V; tr/tf=20 ns; CL=50 pF; RL=200 kΩ; Tamb=25℃ 5
Input capacitance CIN 5 7.5 pF Any input 5

CAD (KiCad official)

  • Symbol: CD4011AMS
  • Footprint: Package_SO:QSOP-16_3.9x4.9mm_P0.635mm
  • 3D model: QSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd4011ams-etched.step / cd4011ams-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4011ams.step / cd4011ams.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HGSEMI datasheet (11 pp, sha256 98a96f3286f5ec45, retrieved 2026-10-18, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF