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CD4010BQDRQ1

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Texas Instruments Buffer/Driver/Transceiver, SOIC-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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CD4010BQDRQ1

Texas Instruments · Buffer/Driver/Transceiver · SOIC-16

CD4010BQDRQ1 from Texas Instruments, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Supply for the output stage, connected to the DTL/TTL supply; recommended range 3 V to VDD.
2 G=A output Buffer output for input A (pin 3), swinging between GND and VCC.
3 A input Buffer input A, protected by the CMOS protection network; input range VCC to VDD.
4 H=B output Buffer output for input B (pin 5), swinging between GND and VCC.
5 B input Buffer input B, protected by the CMOS protection network; input range VCC to VDD.
6 I=C output Buffer output for input C (pin 7), swinging between GND and VCC.
7 C input Buffer input C, protected by the CMOS protection network; input range VCC to VDD.
8 VSS power_in Ground/negative supply reference; all supply voltages are referenced to VSS.
9 D input Buffer input D, protected by the CMOS protection network; input range VCC to VDD.
10 J=D output Buffer output for input D (pin 9), swinging between GND and VCC.
11 E input Buffer input E, protected by the CMOS protection network; input range VCC to VDD.
12 K=E output Buffer output for input E (pin 11), swinging between GND and VCC.
13 NC unconnected No internal connection.
14 F input Buffer input F, protected by the CMOS protection network; input range VCC to VDD.
15 L=F output Buffer output for input F (pin 14), swinging between GND and VCC.
16 VDD power_in CMOS supply voltage, 3 V to 18 V recommended (absolute max -0.5 to +20 V) referenced to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-16
Category Logic ICs
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VDD 3 18 V 3
DC supply voltage range VDD -0.5 20 V voltages referenced to VSS terminal 3
DC input current, any one input -10 10 mA any one input 3
Power dissipation per package PD 500 mW TA = -40°C to +100°C 3
Power dissipation per package at derated temperature PD 200 mW TA = +100°C to +125°C; derate linearly at 12 mW/°C to 200 mW 3
Operating temperature range TA -40 125 °C 3
Storage temperature range Tstg -65 150 °C 3
Latch-up performance 100 mA per JESD 78, Class I 3
ESD human-body model (HBM) 500 V Human-body model (HBM); tested in accordance with AEC-Q100 3
ESD machine model (MM) 100 V Machine model (MM) 3
ESD charged-device model (CDM) 1000 V Charged-Device Model (CDM) 3
Max quiescent device current IDD 1 µA VO=0 V, VIN=5 V, VDD=5 V, +25°C 4
Max quiescent device current IDD 2 µA VO=0 V, VIN=10 V, VDD=10 V, +25°C 4
Max quiescent device current IDD 4 µA VO=0 V, VIN=15 V, VDD=15 V, +25°C 4
Max quiescent device current IDD 20 µA VO=0 V, VIN=20 V, VDD=20 V, +25°C 4
Output voltage low-level VOL 0.05 V VDD=5 V 4
Output voltage high-level VOH 4.95 V VDD=5 V 4
Output voltage high-level VOH 9.95 V VDD=10 V 4
Output voltage high-level VOH 14.95 V VDD=15 V 4
Input low voltage VIL 1.5 V VO=0.5 V, VDD=5 V 4
Input low voltage VIL 3 V VO=1 V, VDD=10 V 4
Input low voltage VIL 4 V VO=1.5 V, VDD=15 V 4
Input high voltage VIH 3.5 V VO=4.5 V, VDD=5 V 4
Input high voltage VIH 7 V VO=9 V, VDD=10 V 4
Input high voltage VIH 11 V VO=13.5 V, VDD=15 V 4
Input current IIN -0.1 0.1 µA VO=0 V, VIN=18 V, VDD=18 V, +25°C 4
Propagation delay time low-to-high tPLH 100 200 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=5 V, VI=5 V, VCC=5 V 5
Propagation delay time low-to-high tPLH 50 100 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=10 V, VI=10 V, VCC=10 V 5
Propagation delay time low-to-high tPLH 35 70 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=15 V, VI=15 V, VCC=15 V 5
Propagation time high-to-low tPHL 65 130 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=5 V, VI=5 V, VCC=5 V 5
Propagation time high-to-low tPHL 35 70 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=10 V, VI=10 V, VCC=10 V 5
Propagation time high-to-low tPHL 30 70 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=10 V, VI=10 V, VCC=5 V 5
Propagation time high-to-low tPHL 25 50 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=15 V, VI=15 V, VCC=15 V 5
Propagation time high-to-low tPHL 20 40 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=15 V, VI=15 V, VCC=5 V 5
Transition time low-to-high tTLH 150 350 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=5 V, VI=5 V, VCC=5 V 5
Transition time low-to-high tTLH 75 150 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=10 V, VI=10 V, VCC=10 V 5
Transition time low-to-high tTLH 55 110 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=15 V, VI=15 V, VCC=15 V 5
Transition time high-to-low tTHL 35 90 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=5 V, VI=5 V, VCC=5 V 5
Transition time high-to-low tTHL 20 45 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=10 V, VI=10 V, VCC=10 V 5
Transition time high-to-low tTHL 15 40 ns TA=25°C, tr/tf=20 ns, CL=50 pF, RL=200 kΩ; VDD=15 V, VI=15 V, VCC=15 V 5
Input capacitance CIN 5 7.5 pF 5

CAD (KiCad official)

  • Symbol: CD4010BQDRQ1
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOIC-16 (KiCad packages3D, STEP)
  • 3D model files: cd4010bqdrq1-etched.step / cd4010bqdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd4010bqdrq1.step / cd4010bqdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (14 pp, sha256 9cde4febc2db0655, retrieved 2026-10-27, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF