component

CD40107BM96

Public Made by Adom

by adom

Texas Instruments Inverters, SOIC-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd40107bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd40107bm96: viewers · Ray
cd40107bm96-etched.fit.json cd40107bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd40107bm96-etched.glb cd40107bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd40107bm96-etched.step cd40107bm96: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd40107bm96.glb Publish 0.1.0 · Ray
cd40107bm96.kicad_mod Publish 0.1.0 · Ray
cd40107bm96.kicad_sym Publish 0.1.0 · Ray
cd40107bm96.lbr Publish 0.1.0 · Ray
cd40107bm96.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json cd40107bm96: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cd40107bm96: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD40107BM96

Texas Instruments · Inverters · SOIC-8

CD40107BM96 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1A input Gate 1 input A. CMOS logic input to the first 2-input NAND stage.
2 1B input Gate 1 input B. CMOS logic input to the first 2-input NAND stage.
3 1C output Gate 1 open-drain NAND output (C = NOT(A AND B)). N-channel open-drain output capable of sinking large currents; requires an external pull-up to the desired load rail. Sink capability typ. tens of mA at VDD=10 V.
4 NC unconnected No internal connection. Leave floating or tie to a convenient net; not internally bonded.
5 2C output Gate 2 open-drain NAND output (C = NOT(A AND B)). N-channel open-drain output capable of sinking large currents; requires an external pull-up to the desired load rail.
6 2B input Gate 2 input B. CMOS logic input to the second 2-input NAND stage.
7 2A input Gate 2 input A. CMOS logic input to the second 2-input NAND stage.
8 VSS power_in Negative supply / ground reference. Typically 0 V.
14 VDD power_in Positive supply voltage, 3 V to 15 V (absolute max 18 V). Bypass with a local ceramic capacitor to VSS.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Logic
Pins 9

Ordering variants

Same part, different packaging or reel option.

  • CD40107BM96
  • CD40107BM96M
  • CD40107BM96E

CAD (KiCad official)

  • Symbol: CD40107BM96
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: cd40107bm96-etched.step / cd40107bm96-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40107bm96.step / cd40107bm96.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd40107bm96.step 122 KB You want the bare part, or you mark your own boards.
cd40107bm96-etched.step 2.4 MB You want the part with CD40107BM96 already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 578 faces against 147 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 85a220a0d1b335ea, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF