component
CD40107BM
Public Made by Adomby adom
Texas Instruments Logic Gates, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCD40107BM
Texas Instruments · Logic Gates · SOIC-8
CD40107BM from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A | input | Gate 1 NAND input A, protected by the COS/MOS network; the input low-level max is 1.5 V at VDD=5 V and the input high-level min is 3.5 V. |
| 2 | B | input | Gate 1 NAND input B, protected by the COS/MOS network; the input low-level max is 1.5 V at VDD=5 V and the input high-level min is 3.5 V. |
| 3 | C | output | Gate 1 open-drain n-channel output (C = NOT(A·B)); it sinks 136 mA typ. at VDD=10 V, VDS=1 V and needs an external pull-up resistor to VDD for a high level. |
| 4 | VSS | power_in | Ground (VSS) supply terminal, 0 V reference for the device. |
| 5 | F | output | Gate 2 open-drain n-channel output (NOT(D·E)); it sinks 136 mA typ. at VDD=10 V, VDS=1 V and needs an external pull-up resistor to VDD for a high level. |
| 6 | E | input | Gate 2 NAND input E, protected by the COS/MOS network; the input low-level max is 1.5 V at VDD=5 V and the input high-level min is 3.5 V. |
| 7 | D | input | Gate 2 NAND input D, protected by the COS/MOS network; the input low-level max is 1.5 V at VDD=5 V and the input high-level min is 3.5 V. |
| 8 | VDD | power_in | Positive supply voltage, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V referenced to VSS. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Logic |
| Pins | 8 |
CAD (KiCad official)
- Symbol:
CD40107BM - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
cd40107bm-etched.step/cd40107bm-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cd40107bm.step/cd40107bm.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (21 pp, sha256
c4aea7a4ac0c1ef8, retrieved 2026-10-01, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).