component

CD40106BE

Public Made by Adom

by adom

Texas Instruments Inverters, DIP-14. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs cd40106be: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers cd40106be: viewers · Ray
cd40106be-etched.fit.json cd40106be: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd40106be-etched.glb cd40106be: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd40106be-etched.step cd40106be: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
cd40106be.glb Publish 0.1.0 · Ray
cd40106be.kicad_mod Publish 0.1.0 · Ray
cd40106be.kicad_sym Publish 0.1.0 · Ray
cd40106be.lbr Publish 0.1.0 · Ray
cd40106be.step Publish 0.1.0 · Ray
package.json Publish 0.2.0 · Ray
page.json cd40106be: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) · Ray
README.md cd40106be: laser-etched CAD + chip hero (factory 2.0.0 backfill) · Ray

CD40106BE

Texas Instruments · Inverters · DIP-14

CD40106BE from Texas Instruments, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A input Schmitt-trigger input to inverter 1 (A). Output appears on pin 2 as A-bar. Positive-going trigger threshold Vp typ 2.9 V at VDD=5 V; negative-going threshold Vn typ 1.9 V at VDD=5 V.
2 ~A output Schmitt-trigger inverter 1 output (logical NOT of A on pin 1). Typical IOL ~1 mA, IOH ~-1 mA at VDD=5 V; standardized symmetrical output characteristics.
3 B input Schmitt-trigger input to inverter 2 (B). Output appears on pin 4 as B-bar. Input current typ 10^-5 uA, max 0.1 uA at VDD=18 V.
4 ~B output Schmitt-trigger inverter 2 output (logical NOT of B on pin 3). Drives standard CMOS loads with symmetrical output characteristics.
5 C input Schmitt-trigger input to inverter 3 (C). Output appears on pin 6 as C-bar. Noise immunity greater than 50%.
6 ~C output Schmitt-trigger inverter 3 output (logical NOT of C on pin 5). Propagation delay tPHL/tPLH typ 140/140 ns at VDD=5 V, 50 pF load.
7 VSS power_in Negative supply / ground reference for the device. All voltages referenced to VSS. Connect to 0 V (system ground).
8 ~D output Schmitt-trigger inverter 4 output (logical NOT of D on pin 9). CMOS push-pull output with no limit on input rise/fall times.
9 D input Schmitt-trigger input to inverter 4 (D). Output appears on pin 8 as D-bar. Maximum input current 1 uA at 18 V over full package-temperature range.
10 ~E output Schmitt-trigger inverter 5 output (logical NOT of E on pin 11). Symmetrical CMOS output; VOL max 0.05 V, VOH min 4.95 V at VDD=5 V.
11 E input Schmitt-trigger input to inverter 5 (E). Output appears on pin 10 as E-bar. Hysteresis provides clean switching on slow input ramps.
12 ~F output Schmitt-trigger inverter 6 output (logical NOT of F on pin 13). Suitable for wave/pulse shaping, monostable and astable multivibrator applications.
13 F input Schmitt-trigger input to inverter 6 (F). Output appears on pin 12 as F-bar. Inputs protected by COS/MOS input protection network.
14 VDD power_in Positive supply voltage. Recommended operating range 3 V to 18 V (absolute max -0.5 V to +20 V relative to VSS). Quiescent IDD typ 0.02 uA at VDD=5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package DIP-14
Category Logic
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • CD40106BEE
  • CD40106BEEE4
  • CD40106BEF
  • CD40106BEF3A
  • CD40106BEM
  • CD40106BEM96
  • CD40106BEMT
  • CD40106BEMG4
  • CD40106BEM96E4
  • CD40106BEM96G4
  • CD40106BEMTG4
  • CD40106BENSR
  • CD40106BENSRG4
  • CD40106BEPW
  • CD40106BEPWR
  • CD40106BEPWG4
  • CD40106BEPWRE4

CAD (KiCad official)

  • Symbol: CD40106BE
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: DIP-14 (KiCad packages3D, STEP)
  • 3D model files: cd40106be-etched.step / cd40106be-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40106be.step / cd40106be.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
cd40106be.step 444 KB You want the bare part, or you mark your own boards.
cd40106be-etched.step 2.4 MB You want the part with CD40106BE already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 593 faces against 250 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (17 pp, sha256 181ef01b1f25785c, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF