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Generated by kicad-footprint-generator · KiCad file format 20260206

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docs	Publish 0.1.0 · Ray	1d ago
viewers	cd40103bnsr: viewers · Ray	1d ago
cd40103bnsr-etched.glb	cd40103bnsr: factory component page (tier=lcsc) · Ray	1d ago
cd40103bnsr-etched.step	cd40103bnsr: factory component page (tier=lcsc) · Ray	1d ago
cd40103bnsr-hero.glb	cd40103bnsr: hero GLB from the etched model (keeps the MPN mark) · Ray	1d ago
cd40103bnsr-hero.overlay.json	Publish 0.1.0 · Ray	1d ago
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README.md	Initial commit: component/cd40103bnsr · Ray	1d ago

CD40103BNSR

Texas Instruments · Counters, Dividers · SO-16

CD40103BNSR from Texas Instruments, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	CLOCK	input	Clock input; the counter decrements by one on each positive clock transition.
2	CLR	input	Active-low clear input; when low, asynchronously clears the counter to its maximum count (255 for the CD40103B) regardless of other inputs.
3	CI/CE	input	Active-low carry-in/counter enable input; counting is inhibited when high.
4	J0	input	Jam (preset) data input J0, the LSB of the 8-bit binary word for the CD40103B.
5	J1	input	Jam (preset) data input J1.
6	J2	input	Jam (preset) data input J2.
7	J3	input	Jam (preset) data input J3.
8	VSS	power_in	Ground (negative supply) reference; all voltages are referenced to VSS.
9	APE	input	Active-low asynchronous preset-enable input; when low, JAM data is forced into the counter regardless of SPE, CI/CE or CLOCK.
10	J4	input	Jam (preset) data input J4.
11	J5	input	Jam (preset) data input J5.
12	J6	input	Jam (preset) data input J6.
13	J7	input	Jam (preset) data input J7, the MSB of the 8-bit binary word for the CD40103B.
14	CO/ZD	output	Active-low carry-out/zero-detect output; goes low when the count reaches zero with CI/CE low and remains low for one full clock period.
15	SPE	input	Active-low synchronous preset-enable input; when low, JAM data is clocked into the counter on the next positive clock transition regardless of the CI/CE state.
16	VDD	power_in	Positive supply; recommended 3 V to 18 V over the full package-temperature range, absolute maximum -0.5 V to +20 V referenced to VSS.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	SO-16
Category	Logic
Pins	16

CAD (KiCad official)

Symbol: CD40103BNSR
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SO-16 (KiCad packages3D, STEP)
3D model files: cd40103bnsr-etched.step / cd40103bnsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40103bnsr.step / cd40103bnsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (21 pp, sha256 1a982876aec1d075, retrieved 2026-10-08, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF