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CD40102BPWR

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Texas Instruments Counters, Dividers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Symbol & Footprint

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Datasheet

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Contents

README

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CD40102BPWR

Texas Instruments · Counters, Dividers · TSSOP-16

CD40102BPWR from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK input Clock input; the counter decrements on each positive clock transition, with a maximum clock pulse rise/fall time of 15 µs at VDD = 10 V.
2 CLR input Active-low asynchronous clear; when low it clears the counter to its maximum count (99 for CD40102B, 255 for CD40103B) regardless of other inputs.
3 CI/CE input Active-low carry-in/counter enable input; counting is inhibited when high.
4 J0 input Jam (preset) data input 0, the LSB of the preset word.
5 J1 input Jam (preset) data input 1.
6 J2 input Jam (preset) data input 2.
7 J3 input Jam (preset) data input 3, the MSB of the lower BCD decade on the CD40102B.
8 VSS power_in Ground (VSS) supply terminal, the reference for all voltages.
9 APE input Active-low asynchronous preset enable; when low, JAM data is forced into the counter regardless of SPE, CI/CE or CLOCK.
10 J4 input Jam (preset) data input 4, the LSB of the upper BCD decade on the CD40102B.
11 J5 input Jam (preset) data input 5.
12 J6 input Jam (preset) data input 6.
13 J7 input Jam (preset) data input 7, the MSB of the preset word.
14 CO/ZD output Active-low carry-out/zero-detect output; goes low when the count reaches zero with CI/CE low and stays low for one full clock period.
15 SPE input Active-low synchronous preset enable; when low, JAM data is clocked into the counter on the next positive clock transition.
16 VDD power_in Positive supply voltage, recommended 3 V to 18 V, absolute maximum -0.5 V to +20 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD40102BPWR
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: cd40102bpwr-etched.step / cd40102bpwr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40102bpwr.step / cd40102bpwr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 1a982876aec1d075, retrieved 2026-10-07, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF