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CD40102BNSR
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Texas Instruments Counters, Dividers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# CD40102BNSR++**Texas Instruments** · Counters, Dividers · SO-16++CD40102BNSR from Texas Instruments, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | CLOCK | input | Clock input; the counter decrements on each positive clock transition, with a maximum clock rise/fall time of 15 µs at VDD = 10 V. |+| 2 | CLR | input | Active-low asynchronous clear input that sets the counter to its maximum count (99 for CD40102B) regardless of all other inputs. |+| 3 | CI/CE | input | Active-low carry-in/counter enable input; counting is inhibited when this input is high. |+| 4 | J0 | input | Jam (preset) data input bit 0, the LSB of the lower BCD decade (J3-J0) on the CD40102B. |+| 5 | J1 | input | Jam (preset) data input bit 1 of the lower BCD decade. |+| 6 | J2 | input | Jam (preset) data input bit 2 of the lower BCD decade. |+| 7 | J3 | input | Jam (preset) data input bit 3, the MSB of the lower BCD decade (J3-J0). |+| 8 | VSS | power_in | Ground (VSS) supply terminal, the reference for the -0.5 V to +20 V VDD absolute maximum rating. |+| 9 | APE | input | Active-low asynchronous preset-enable input; when low the JAM data is forced into the counter regardless of SPE, CI/CE or CLOCK. |+| 10 | J4 | input | Jam (preset) data input bit 4, the LSB of the upper BCD decade (J7-J4). |+| 11 | J5 | input | Jam (preset) data input bit 5 of the upper BCD decade. |+| 12 | J6 | input | Jam (preset) data input bit 6 of the upper BCD decade. |+| 13 | J7 | input | Jam (preset) data input bit 7, the MSB of the upper BCD decade (J7-J4). |+| 14 | CO/ZD | output | Active-low carry-out/zero-detect output that goes low when the count reaches zero with CI/CE low and stays low for one full clock period. |+| 15 | SPE | input | Active-low synchronous preset-enable input; when low, JAM data is clocked into the counter on the next positive clock transition. |+| 16 | VDD | power_in | Positive supply voltage, recommended range 3 V to 18 V over the full package-temperature range (absolute maximum -0.5 V to +20 V). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | SO-16 |+| Category | Logic |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `CD40102BNSR`+- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`+- 3D model: SO-16 (KiCad packages3D, STEP)+- 3D model files: `cd40102bnsr-etched.step` / `cd40102bnsr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cd40102bnsr.step` / `cd40102bnsr.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/cd40103b) (21 pp, sha256 `1a982876aec1d075`, retrieved 2026-10-07, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cd40102bnsr-datasheet.pdf)
page.jsonadded+248@@ -0,0 +1,248 @@+{+ "slug": "cd40102bnsr",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments Counters, Dividers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "logic",+ "cd40102bnsr",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cd40102bnsr.kicad_sym",+ "cd40102bnsr.kicad_mod",+ "cd40102bnsr.glb",+ "cd40102bnsr.step",+ "cd40102bnsr.lbr",+ "docs/hero.png",+ "docs/cd40102bnsr-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cd40102bnsr-hero.glb",+ "cd40102bnsr-hero.overlay.json"+ ],+ "component": {+ "mpn": "CD40102BNSR",+ "manufacturer": "Texas Instruments",+ "package": "SO-16",+ "pin_count": 16,+ "category": "Logic",+ "subcategory": "Counters, Dividers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/cd40103b",+ "parts": {+ "symbol": "cd40102bnsr.kicad_sym",+ "footprint": "cd40102bnsr.kicad_mod",+ "model_3d": "cd40102bnsr-hero.glb",+ "model_3d_plain": "cd40102bnsr.glb",+ "model_3d_step": "cd40102bnsr-etched.step",+ "model_3d_step_plain": "cd40102bnsr.step",+ "lbr": "cd40102bnsr.lbr"+ },+ "distributor_links": {+ "lcsc": "C1879802",+ "digikey": "296-CD40102BNSRTR-ND",+ "mouser": "595-CD40102BNSR"+ },+ "distributor_check": {+ "checked_at": "2026-10-07T01:52:01Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-CD40102BNSRTR-ND",+ "status": "found"+ },+ "mouser": {+ "pn": "595-CD40102BNSR",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "CLOCK",+ "type": "input",+ "description": "Clock input; the counter decrements on each positive clock transition, with a maximum clock rise/fall time of 15 µs at VDD = 10 V."+ },+ {+ "number": "2",+ "name": "CLR",+ "type": "input",+ "description": "Active-low asynchronous clear input that sets the counter to its maximum count (99 for CD40102B) regardless of all other inputs."+ },+ {+ "number": "3",+ "name": "CI/CE",+ "type": "input",+ "description": "Active-low carry-in/counter enable input; counting is inhibited when this input is high."+ },+ {+ "number": "4",+ "name": "J0",+ "type": "input",+ "description": "Jam (preset) data input bit 0, the LSB of the lower BCD decade (J3-J0) on the CD40102B."+ },+ {+ "number": "5",+ "name": "J1",+ "type": "input",+ "description": "Jam (preset) data input bit 1 of the lower BCD decade."+ },+ {+ "number": "6",+ "name": "J2",+ "type": "input",+ "description": "Jam (preset) data input bit 2 of the lower BCD decade."+ },+ {+ "number": "7",+ "name": "J3",+ "type": "input",+ "description": "Jam (preset) data input bit 3, the MSB of the lower BCD decade (J3-J0)."+ },+ {+ "number": "8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground (VSS) supply terminal, the reference for the -0.5 V to +20 V VDD absolute maximum rating."+ },+ {+ "number": "9",+ "name": "APE",+ "type": "input",+ "description": "Active-low asynchronous preset-enable input; when low the JAM data is forced into the counter regardless of SPE, CI/CE or CLOCK."+ },+ {+ "number": "10",+ "name": "J4",+ "type": "input",+ "description": "Jam (preset) data input bit 4, the LSB of the upper BCD decade (J7-J4)."+ },+ {+ "number": "11",+ "name": "J5",+ "type": "input",+ "description": "Jam (preset) data input bit 5 of the upper BCD decade."+ },+ {+ "number": "12",+ "name": "J6",+ "type": "input",+ "description": "Jam (preset) data input bit 6 of the upper BCD decade."+ },+ {+ "number": "13",+ "name": "J7",+ "type": "input",+ "description": "Jam (preset) data input bit 7, the MSB of the upper BCD decade (J7-J4)."+ },+ {+ "number": "14",+ "name": "CO/ZD",+ "type": "output",+ "description": "Active-low carry-out/zero-detect output that goes low when the count reaches zero with CI/CE low and stays low for one full clock period."+ },+ {+ "number": "15",+ "name": "SPE",+ "type": "input",+ "description": "Active-low synchronous preset-enable input; when low, JAM data is clocked into the counter on the next positive clock transition."+ },+ {+ "number": "16",+ "name": "VDD",+ "type": "power_in",+ "description": "Positive supply voltage, recommended range 3 V to 18 V over the full package-temperature range (absolute maximum -0.5 V to +20 V)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "vision",+ "consensus_model": "claude-opus-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet shows a single terminal-assignment diagram (page 6) for the 16-lead packages of CD4010",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 12,+ "cost_usd": 0.4123,+ "at": "2026-10-07T01:51:44"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/cd40103b",+ "pages": 21,+ "sha256": "1a982876aec1d075",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cd40102bnsr.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d5eeddb4c0b304dc61950919b126fc61d7586abd5f16ab71a2a79759ec6498bf",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cd40102bnsr-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6,+ 9.9,+ 1.75+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "980c92f147028d642af78b3a8e4f808ae27af057d149c232a13337271ee746f7",+ "checked": "2026-10-07",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}