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CD40102BNSR

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Texas Instruments Counters, Dividers, SO-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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CD40102BNSR

Texas Instruments · Counters, Dividers · SO-16

CD40102BNSR from Texas Instruments, in a SO-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CLOCK input Clock input; the counter decrements on each positive clock transition, with a maximum clock rise/fall time of 15 µs at VDD = 10 V.
2 CLR input Active-low asynchronous clear input that sets the counter to its maximum count (99 for CD40102B) regardless of all other inputs.
3 CI/CE input Active-low carry-in/counter enable input; counting is inhibited when this input is high.
4 J0 input Jam (preset) data input bit 0, the LSB of the lower BCD decade (J3-J0) on the CD40102B.
5 J1 input Jam (preset) data input bit 1 of the lower BCD decade.
6 J2 input Jam (preset) data input bit 2 of the lower BCD decade.
7 J3 input Jam (preset) data input bit 3, the MSB of the lower BCD decade (J3-J0).
8 VSS power_in Ground (VSS) supply terminal, the reference for the -0.5 V to +20 V VDD absolute maximum rating.
9 APE input Active-low asynchronous preset-enable input; when low the JAM data is forced into the counter regardless of SPE, CI/CE or CLOCK.
10 J4 input Jam (preset) data input bit 4, the LSB of the upper BCD decade (J7-J4).
11 J5 input Jam (preset) data input bit 5 of the upper BCD decade.
12 J6 input Jam (preset) data input bit 6 of the upper BCD decade.
13 J7 input Jam (preset) data input bit 7, the MSB of the upper BCD decade (J7-J4).
14 CO/ZD output Active-low carry-out/zero-detect output that goes low when the count reaches zero with CI/CE low and stays low for one full clock period.
15 SPE input Active-low synchronous preset-enable input; when low, JAM data is clocked into the counter on the next positive clock transition.
16 VDD power_in Positive supply voltage, recommended range 3 V to 18 V over the full package-temperature range (absolute maximum -0.5 V to +20 V).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SO-16
Category Logic
Pins 16

CAD (KiCad official)

  • Symbol: CD40102BNSR
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SO-16 (KiCad packages3D, STEP)
  • 3D model files: cd40102bnsr-etched.step / cd40102bnsr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cd40102bnsr.step / cd40102bnsr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (21 pp, sha256 1a982876aec1d075, retrieved 2026-10-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF